Patent US564707A successfully refreshed from Google Patents.
Patent EP0083089A2 successfully refreshed from Google Patents.
EP0083089A2
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EP
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Process for forming self-aligned metallization patterns for semiconductor devices
Assignee: International Business Machines Corp
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Filing: 1982-12-27
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Granted: —
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Expires: 2002-12-27
Abstract
Abstract A process is described which achieves self-aligned contacts and electrodes (42, 44, 46) having very close spacing in integrated circuit devices by use of a pattern of dielectric material (30) having a thickness in the order of a micrometer or less. A pattern of recessed oxide isolation (32) between device areas in the substrate (10) is also self-aligned by this process. The result is a substantial planar integrated circuit structure. The process is applicable to either bipolar transistor integrated circuits or MOS field effect transistor integrated circuits.
Inventors
- 👤 Shakir Ahmed Abbas
- 👤 Ingrid Emese Magdo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:02
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P76/00; H10P76/40; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/075; H10W20/40; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
288 words
Method for forming self-aligned metallization for semiconductor devices comprising the following steps: forming a first insulating layer (22; 56) on the surface of a monocrystalline silicon substrate (10, 45), whose coefficient of expansion is similar to that of the substrate; forming a second insulating layer (24; 58) over said first layer; forming a polycrystalline silicon layer (26; 52) over said second layer; forming a third insulating layer (27; 54) over said polycrystalline silicon layer; removing said third insulating layer and said polycrystalline silicon layer down to said second insulating layer to produce substantially vertical sidewalls on the remaining third insulating layer and polycrystalline silicon layer; wherein the said removing of said third insulating layer and polycrystalline silicon layer is in areas designated to be at least source/drain regions of field effect transistor devices or emitter regions of bipolar devices; thermally oxidizing the exposed sidewalls of said polycrystalline silicon layer to produce a silicon dioxide sidewall layer (30; 60; 69; 70) thereon; removing the exposed said second insulating layer; forming the source/drain regions (62; 74) or the emitters (34), respectively, in the areas of said silicon substrate under the removed portions; removing the remaining said third insulating and polycrystalline silicon layers to leave the remaining portions of said silicon dioxide sidewall layer extending above said silicon substrate; forming openings in said first insulating layer to the elements of said field effect transistor devices or bipolar devices, respectively; and forming a substantially planar conductive layer (40, 42, 44, 46; 64, 66, 68; 76, 78, 80) on said silicon body which has portions thereof electrically separated by said silicon dioxide sidewall layer (30; 60; 69, 70), for contacting the said elements of said field effect transistor devices or bipolar devices, respectively.
Claim 2
Dependent Claim
288 words
Method for forming self-aligned metallization for semiconductor devices comprising the following steps: forming a first insulating layer (22; 56) on the surface of a monocrystalline silicon substrate (10, 45), whose coefficient of expansion is similar to that of the substrate; forming a second insulating layer (24; 58) over said first layer; forming a polycrystalline silicon layer (26; 52) over said second layer; forming a third insulating layer (27; 54) over said polycrystalline silicon layer; removing said third insulating layer and said polycrystalline silicon layer down to said second insulating layer to produce substantially vertical sidewalls on the remaining third insulating layer and polycrystalline silicon layer; wherein the said removing of said third insulating layer and polycrystalline silicon layer is in areas designated to be at least source/drain regions of field effect transistor devices or emitter regions of bipolar devices; thermally oxidizing the exposed sidewalls of said polycrystalline silicon layer to produce a silicon dioxide sidewall layer (30; 60; 69; 70) thereon; removing the exposed said second insulating layer; forming the source/drain regions (62; 74) or the emitters (34), respectively, in the areas of said silicon substrate under the removed portions; removing the remaining said third insulating and polycrystalline silicon layers to leave the remaining portions of said silicon dioxide sidewall layer extending above said silicon substrate; forming openings in said first insulating layer to the elements of said field effect transistor devices or bipolar devices, respectively; and forming a substantially planar conductive layer (40, 42, 44, 46; 64, 66, 68; 76, 78, 80) on said silicon body which has portions thereof electrically separated by said silicon dioxide sidewall layer (30; 60; 69, 70), for contacting the said elements of said field effect transistor devices or bipolar devices, respectively.
Claim 3
Dependent Claim
29 words
A method in accordance with claim 1, characterized in that said silicon dioxide sidewall layer (30; 60; 69, 70) has a thickness of between about 0.6 to 2 micrometers.
Claim 4
Dependent Claim
38 words
A method in accordance with claim 1, characterized in that said first insulating layer (22; 56) is silicon dioxide, said second insulating layer (24; 58) is silicon nitride, and said third insulating layer (27; 54) is silicon dioxide.
Claim 5
Dependent Claim
33 words
A method in accordance with claim 1, characterized in that said steps of removing said third insulating layer (27; 54) and said polycrystalline silicon layer (26; 52) are effected by anisotropic etching process.
Claim 6
Dependent Claim
27 words
A method in accordance with claim 1, characterized in that said conductive layer (40, 42, 44, 46; 64, 66, 68; 76, 78, 80) is composed of aluminium.
Claim 7
Dependent Claim
42 words
A method in accordance with claim 1, characterized in that the step of forming source/drain regions (62; 74) is effected by ion implantation of N- type conductivity imparting impurities into said monocrystalline silicon substrate (45), thus producing N channel field effect transistors.
Claim 8
Dependent Claim
71 words
A method in accordance with claim 1, characterized in that prior to forming said first insulating layer (22), bipolar transistor regions are prepared by forming in said monocrystalline silicon substrate (12) P-type base regions (20) and N- type subcollector with collector reach through regions (18), and that the step of forming emitters (34) is effected by ion implantation of conductivity imparting impurities into said base regions (20) thus producing NPN transistors.
Claim 9
Dependent Claim
18 words
A method in accordance with claim 6 or 7, characterized in that said conductivity imparting impurities are arsenic.
Claim 10
Dependent Claim
155 words
A method in accordance with claim 1, characterized in that for forming self-aligned isolation areas (32) for separating semiconductor devices, the following additional steps are performed: after forming said third insulating layer (27), this third insulating layer and the polycrystalline silicon layer (26) are removed down to said second insulating layer (24) in areas (28) designated to be the isolation areas; the then exposed sidewalls of said polycrystalline silicon layer are oxidized to produce a silicon dioxide sidewall layer thereon; the exposed second insulating layer (24) and in turn the exposed first insulating layer (22) are removed; openings are etched into the then exposed monocrystalline silicon substrate (12) using the remaining third insulating layer and polycrystalline silicon layer as a mask; and the openings are filled with dielectric isolation material (32). 10. A method in accordance with claim 9, characterized in that said dielectric isolation (32) is between about 0.3 to 1 micrometers in depth.
References Cited (Backward Citations)
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