Address generator

Claim 2

An address generator for generating addresses enabling a memory device (12) to store data and to output stored data in a predetermined sequence in response to X and Y starting addresses and first and second incremental X and Y correction values received from a computer (14) and pixel signals received from a timing signal generator (22) characterized in that such address generator comprises: X axis address generator means (100, 102, 108, 110, 116, 118, 124) for sequentially generating X addresses in response to the X starting address, the first incremental X correction the first incremental Y correction value and the pixel and line strobe signals; Y axis address generator means (104, 106, 112, 114, 120, 122, 126) for sequentially generating Y axis addresses in response to the Y starting address, the second incremental X correction value, the second incremental Y correction value and the pixel and line strobe signals; and decoder means (25) responsive to the address on the computer's (14) address bus for generating said line strobe signals in a predetermined sequential order.

Claim 3

The address generator of Claim 1 characterized in that said X axis generator means comprises: first means (100, 108, 116) for repetitively adding the first incremental Y correction value to the X starting address in response to said line strobe signals to generate a line corrected X address having a value equal to said X starting address plus N times said first incremental Y value where N is the number of received line strobe signals; second means (102, 110, 118) for repetitively adding the first incremental X correction value to itself in response to said pixel strobe signals to generate a first address correction having a value equal to M times the first incremental X correction value; third means (124) for summing said line corrected X address with said first X address correction to generate said X addresses; and wherein said Y axis generator means comprises: fourth means (104, 112, 120) for repetitively adding the second incremental Y correction value to said Y starting address in response to said line strobe signals to generate a line corrected Y address having a value equal to the Y starting address plus N times the second incremental Y correction value where N is the number of rprpived line strobe signals; fifth means (106, 114, 122) for repetitively adding the second incremental X correction value to itself to generate a second address correction having a value equal to M times incremental X correction value where M is the number of received pixel strobe signals; sixth means (126) for summing said line corrected Y address with said second address correction to generate said Y addresses.

Claim 4

The address generator of Claim 2 characterized in that the address on the computer's address bus is indicative of the data present on the computer's data bus, said first means (100, 102, 108, 110, 116, 118, 124, 125) comprises: first register means (100) connected to the computer's data bus for sequentially receiving and storing the X starting address and the first incremental Y correction value generated by the computer in response to a first and third register strobe signal; second register means (116) for storing said X starting address in response to a second register strobe signal and said line corrected X address in response to the line strobe signals; and a first adder (108) connected between said first and second register means (100, 116) for summing the content of said first and second register means (100, 116) to generate said X starting address and line corrected X address stored in said second register means (116); and wherein said second means comprises: third register means (102) connected to the computer's data bus for receiving and storing said first incremental X correction value in response to a fourth register strobe signal; fourth register means (118) for storing said first address correction in response to the pixel strobe signals; and .a second adder (110) connected between said third and fourth register means (102, 118) for summing the content of said third and fourth register mean (102, 108) to generate said first address correction stored in said fourth register means (118).

Claim 5

The address generator of Claim 3 characterized in that the address in the computer's address bus is indicative of the data present on the computers data bus, said fourth means (104, 112, 120) comprises: fifth register means (104) connected to the computer's .data bus for sequentially receiving and storing the Y starting address and the second incremental Y correction value generated by the computer (114) in response to a fifth and seventh register strobe signal respectively; sixth register means (120) for storing said Y starting address in response to a sixth register strobe signal and said line corrected Y address in response to said line strobe signals; . a third adder (112) connected between said fifth and sixth register means (104, 120) for summing the content of said fifth and sixth registers (104, 120) to generate said line corrected Y address stored in said sixth register means (120); and wherein said fifth means (106, 114, 122) comprises: seventh register means (106) connected to the computer's data bus for storing the second incremental X correction value generated by the computer (114) in response to an eighth register strobe signal; eighth register means (122) for storing said second address correction in response to the pixel strobe signals; a fourth adder (114) connected between said seventh and eighth register means (106, 122) for summing the content of said seventh and eighth register means (106, 122) to generate said second address correction stored in said eighth register means (122).

Claim 6

The address generator of Claims 1 or 4 characterized in that said memory (12) has a plurality of memory elements disposed at the intersections of orthogonal rows and columns and wherein Δ X is a distance between adjacent storage elements along said rows, and Δ Y is a distance between adjacent storage elements along said columns and Ψ is an angular displacement of the parallel lines along which the addresses are to be generated, where the angle Ψ is measured with respect to said rows, the computer (14) generates said first and second incremental X values according to the equations said first incremental X value = k Δ X cos Ψ said second incremental X value = - k Δ X sin Ψ and generates said first and second incremental Y values according to the equations: said first incremental Y value = K Δ Y sin said second incremental Y value = K Δ Y cosy where k and K are predetermined constants.