Patent EP0082682A2 successfully refreshed from Google Patents.
EP0082682A2
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Microcomputer unit
Assignee: Fujitsu Ltd
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Filing: 1982-12-16
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Granted: —
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Expires: 2002-12-16
Abstract
Abstract A microcomputer unit containing therein a plurality of registers with address allotted in advance. The registers can be accessed for monitoring by an external address signal when the allotted address thereof and the external address signal coincide with each other. In this case, operation of the microcomputer is stopped by an external HALT signal and then the content of the register to be monitored is read by a monitor (MNT) signal so that the content thereof is fed externally from the microcomputer unit.
Inventors
- 👤 Tetsuo Suzuki
- 👤 Senji Nishikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:50
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656; G06F11/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
125 words
A microcomputer unit comprising: a plurality of registers allotted an address respectively; a bus line connected to the registers; a port means connected to external pins of the microcomputer unit for communication between the inside and outside of the microcomputer unit; a first terminal for receiving an external HALT signal for holding an operation of the microcomputer unit; a second terminal-for receiving a monitor (MNT) signal; and control circuits provided at each of said registers for detecting whether or not an address signal on said bus line coincides with the address allotted to the register to be monitored and transferring a content of the register corresponding to the address signal, via said bus line, to the port means in response to said monitor (MNT) signal.
Claim 2
Dependent Claim
125 words
A microcomputer unit comprising: a plurality of registers allotted an address respectively; a bus line connected to the registers; a port means connected to external pins of the microcomputer unit for communication between the inside and outside of the microcomputer unit; a first terminal for receiving an external HALT signal for holding an operation of the microcomputer unit; a second terminal-for receiving a monitor (MNT) signal; and control circuits provided at each of said registers for detecting whether or not an address signal on said bus line coincides with the address allotted to the register to be monitored and transferring a content of the register corresponding to the address signal, via said bus line, to the port means in response to said monitor (MNT) signal.
Claim 3
Dependent Claim
45 words
A microcomputer unit as set forth in claim 1, wherein said port means comprises a first port for receiving an address signal for specifying a desired register to be monitored, and a second port for outputting the content read from the register to be monitored.
Claim 4
Dependent Claim
55 words
A microcomputer unit as set forth in claim 2, wherein each of said control circuits is comprised of at least an address decoder receiving said external address signal, transferred on the bus line, and producing a selection signal to the corresponding register so that the content of this register is fed to said bus line.
Claim 5
Dependent Claim
71 words
A microcomputer unit as set forth in claim 3, wherein said register is provided with, at its output, first transfer gates; said address decoder is provided with, at its output, a 2-input AND gate, which output controls the on and off operation of the first transfer gates; the 2-input AND gate receiving, at one input, said selection signal and, at the other input, a data read enable signal S DRE .
Claim 6
Dependent Claim
55 words
A microcomputer unit as set forth in claim 4, wherein said first port is connected, via second transfer gates, to said bus line, the bus line is connected, via third transfer gates, to said address decoder, and the second and third transfer gates are made on and off by an address latch enable signal SALE.
Claim 7
Dependent Claim
42 words
A microcomputer unit as set forth in claim 5, wherein said bus line is connected, via fourth transfer gates, to said second port, and the fourth transfer gates are made on and off by said data read enable signal S DRE .
Claim 8
Dependent Claim
70 words
A microcomputer unit as set forth in claim 6, wherein said fourth transfer gates are connected, via switchers, to said second port, the switchers are controlled by a data output enable signal S DOE , and the switchers transfer said content of the register to be monitored and an instruction fetch address signal IFADD which is an address of an instruction to be executed next after completion of a monitor.
Claim 9
Dependent Claim
68 words
A microcomputer unit as set forth in claim 7, wherein first said HALT signal is externally supplied, second said external address signal is supplied, third said MNT signal is externally supplied, fourth said signal SALE is generated in the microcomputer unit, fifth said signal S SL is generated therein, sixth said signal S DRE is generated therein, and seventh said signal S DOE is g en- erated therein.
Claim 10
Dependent Claim
38 words
A microcomputer unit as set forth in claim 2, wherein said first port for receiving said external address signal and said second port for producing the content of the register to be monitored are common and activated alternately.
References Cited (Backward Citations)
No citation records indexed.
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