Patent EP0081999A2 successfully refreshed from Google Patents.
EP0081999A2
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EP
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A method of fabricating a MOS transistor on a substrate
Assignee: Inmos Corp
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Filing: 1982-12-10
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Granted: —
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Expires: 2002-12-10
Abstract
Abstract The invention relates to fabrication techniques for the construction of MOS transistors to provide source/drain regions (20, 22) which are self-aligned and non-overlapping with respect to their gate electrode (16). The non-over-lapping feature is provided by defining a gate electrode (16) over a substrate (10), forming an implant mask of dielectric (18), for example, on the sides of the gate electrode (16), and implanting a source/drain region (20, 22) such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode (16) and the implanted regions (20, 22). The source/drain region (20, 22) is then heat driven until its side edge is substantially aligned with the edge of the gate electrode (16). Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.
Inventors
- 👤 William D. Ryden
- 👤 Matthew V. Hanson
- 👤 Gary F. Derbenwick
- 👤 Alfred P. Gnadinger
- 👤 James R. Adams
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:52
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/60; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10P30/208; H10P30/21; H10P30/212; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
141 words
A method of fabricating on a substrate a MOS transistor having a gate electrode and at least one source/drain electrode, comprising forming a gate electrode (16) insulated from the substrate (10), forming an implant mask (18) of a controlled width on the sides of the gate electrode (16), implanting at least one source/drain region (20, 22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap between a side edge of the gate electrode (16) and a side edge of the implanted region (20, 22), and heat driving the implanted source/drain region (20, 22) until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16), whereby no substantial gap or overlap exists between the source/drain region and the gate electrode.
Claim 2
Independent Claim
141 words
A method of fabricating on a substrate a MOS transistor having a gate electrode and at least one source/drain electrode, comprising forming a gate electrode (16) insulated from the substrate (10), forming an implant mask (18) of a controlled width on the sides of the gate electrode (16), implanting at least one source/drain region (20, 22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap between a side edge of the gate electrode (16) and a side edge of the implanted region (20, 22), and heat driving the implanted source/drain region (20, 22) until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16), whereby no substantial gap or overlap exists between the source/drain region and the gate electrode.
Claim 3
Dependent Claim
80 words
A method as claimed in Claim 1, wherein said implant mask is formed by establishing a dielectric (18) on the top and sides of the gate electrode (16) and over the substrate (10) adjacent the gate electrode such that the dielectric (18) on the top and sides of the gate electrode (16) is relatively thick compared to the dielectric over the substrate, whereby source/drain implantation is masked by the relatively thick dielectric (B) on the sides of the gate electrode.
Claim 4
Dependent Claim
46 words
A method as claimed in Claim 2, wherein said dielectric (18) comprises an oxide which is grown at a differential rate to provide a relatively thin oxide layer over the substrate and a relatively thicker oxide on the top and sides of the gate electrode (16).
Claim 5
Dependent Claim
20 words
A method as claimed in Claim 3, wherein the oxide is grown in steam at a temperature of about 850°C.
Claim 6
Dependent Claim
25 words
A method as claimed in Claim 3, wherein the source/ drain region (20, 22) is implanted through the relatively thin oxide layer over the substrate.
Claim 7
Dependent Claim
45 words
A method as claimed in Claim 2, including anisotropically etching the dielectric (18) prior to implanting the source/drain region (20, 22) so as to remove dielectric over the intended source/drain region and yet maintain masking dielectric (B) on the sides of the gate electrode (16).
Claim 8
Independent Claim
136 words
A method as claimed in any one of Claims 1 to 6, including forming an intermediate dielectric (24) over the gate electrode (16) and over the source/drain region (20, 22), patterning a contact area over the source/drain region (20, 22) so that the contact area overlies the source/drain region and overlaps the implant mask on the gate electrode (16), etching the contact area down to the substrate (10) while leaving the implant mask (18) on the sides and top of the gate electrode (16), and providing a conductive material-(32, 34) in the etched contact area to provide a contact for the source/drain region (20, 22) whereby a self-aligned contact is formed such that the gate electrode (16) is prohibited by the implant mask (18) from being shorted in the event the patterned contact area is misaligned.
Claim 9
Dependent Claim
98 words
A method as claimed in Claim 1, wherein the implant mask is formed by forming a first dielectric (42) on the top of the gate electrode (40), forming a second dielectric (44) over the first dielectric (42), over the sides of the gate electrode, and over the intended source/drain region (20a, 22a), and etching the second dielectric (44) where it overlies the intended drain/source region, whereby the second dielectric formed on the sides of the gate electrode (40) comprises the implant mask and the source/drain regions may be implanted at the etched portion of the second dielectric (44).
Claim 10
Dependent Claim
66 words
A method as claimed in Claim 1, wherein the implant mask is formed by forming a dielectric (46) over the gate electrode (16b) and over the intended source/drain region (20b, 22b), and anisotropically etching the dielectric (46) at the top of the gate electrode (16b) and the intended source/drain region so as to leave dielectric remnants (46a, 46b) on the sides of the gate electrode (16b).
Claim 11
Dependent Claim
38 words
A method as claimed in Claim 9, wherein the source/ drain region (20b, 22b) is implanted while the top of the gate electrode (16b) is substantially free of dielectric for doping the gate electrode (16b) during source/drain implantation.
Claim 12
Dependent Claim
38 words
A method as claimed in Claim 9 or Claim 10, wherein a relatively thin oxide (48) is formed over the gate electrode (16b), the dielectric remnants (46a, 46b) and the intended source/drain region (20b, 22b) prior to implantation.
Claim 13
Dependent Claim
15 words
A method as claimed in Claim 1, wherein said implant mask_comprises photoresist remnants (50a, 50b).
Claim 14
Dependent Claim
99 words
A method as claimed in Claim 12, wherein said photoresist remnants are established by placing a conforming layer of photoresist (50) over the gate electrode (16c) and over the intended source/drain region (20c, 22c) such that a greater depth (I) of photoresist occurs adjacent the edges of the gate electrode (16c) than over the top of the gate electrode and over other areas of the intended source/drain region, and removing photoresist from the top of the gate electrode and from the source/drain region so as to leave photoresist remnants (50a, 50b) on the sides of the gate electrode (16c).
Claim 15
Dependent Claim
33 words
A method as claimed in Claim 13, including forming an oxide layer over the gate electrode prior to the application of the photoresist to prevent doping of the gate electrode during source/drain implant.
Claim 16
Dependent Claim
241 words
A method as claimed in Claim 1, of fabricating on a substrate a MOS transistor having a gate electrode and a pair of source/drain regions, comprising forming a relatively thin gate insulator (14) over the substrate (10) and over the intended source/drain regions (20, 22), defining a polysilicon gate electrode (16) over the gate insulator (14) between the intended source/drain regions (20, 22), establishing a dielectric layer (18) over the gate electrode (16) and the gate insulator (14) such that the dielectric (18) is relatively thick at least over the sides of the gate electrode (16) and relatively thinner over the intended source/drain regions (20, 22), implanting the source/drain regions (20, 22) such that they are laterally offset from the substrate area below the gate electrode (16) by the thickness of the dielectric layer (18) on the sides of the gate electrode (16), heat driving the source/drain regions (20, 22) laterally until their edges are substantially vertically aligned with the sides of the gate electrode (16), etching contact areas so as to lay bare the substrate (10) holding the source/drain regions (20, 22) and yet maintaining the dielectric (18) on the sides of the gate electrode (16), and forming conductive contacts (32, 34) in the etched areas, whereby the source/drain regions (20, 22) are properly aligned with the gate electrode (16) and the metal contacts (32, 34) are aligned with the source/drain regions (20, 22) without shorting the gate electrode (16).
References Cited (Backward Citations)
No citation records indexed.
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