Static memory cell

Abstract

Abstract Static memory cell, including two fed-back inverters each having a switching transistor having drain, source and gate electrodes, a load element in the form of a depletion transistor having drain, source and gate electrodes, an output node connected to the drain electrode of the switching transistor and the gate electrode of the depletion transistor, and an additional potential source connected between the output node and the source electrode of the depletion transistor.

Inventors

• 👤 Cosimo Dr. Scianna

Bibliographic Details