Patent EP0080935A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0080935A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Dynamic semiconductor memory device

Assignee: Fujitsu Ltd
•
Filing: 1982-11-24
•
Granted: —
•
Expires: 2002-11-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A dynamic semiconductor memory device provides a selected real cell which is connected to one of a pair of bit lines connected to a sense amplifier and a dummy cell which is connected to the other bit line so as to perform the read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation, or a write circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the read cell is tested, an optional power source can be applied from the test power source pad instead of from a normal power source.

Inventors

  • 👤 Yoshihiro Takemae
  • 👤 Tsuyoshi Kurashi-No-Kyoshitsu 102 Ohira
  • 👤 Seiji Enomoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 21:34
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/026; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C29/04; G11C29/50; G11C2029/5004

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 130 words
A dynamic semiconductor memory device where a selected real cell is connected to one of a pair of bit lines connected to a sense amplifier and a dummy cell is connected to the other bit lines to perform the read-out operation, said dynamic semiconductor memory device being characterized in that a test power source pad is mounted on an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by said read-out operation, or on a write-in circuit for charging the selected real cell through said bit line so that an optional power source voltage can be applied from said pad instead of from a normal power source.
Claim 2
Dependent Claim 130 words
A dynamic semiconductor memory device where a selected real cell is connected to one of a pair of bit lines connected to a sense amplifier and a dummy cell is connected to the other bit lines to perform the read-out operation, said dynamic semiconductor memory device being characterized in that a test power source pad is mounted on an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by said read-out operation, or on a write-in circuit for charging the selected real cell through said bit line so that an optional power source voltage can be applied from said pad instead of from a normal power source.
Claim 3
Dependent Claim 69 words
A dynamic semiconductor memory device according to claim 1, wherein, when said dynamic semiconductor memory device is tested, said power source for normal operation is disconnected, a voltage lower than said power source is supplied to said test power source pad, and operation and a read-out operation in said real cell are repeated while decreasing the voltage so as to determine the minimum voltage level of said real cell.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag