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EP0080354A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Computer memory checking system

Assignee: Unisys Corp
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Filing: 1982-11-22
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Granted: —
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Expires: 2002-11-22
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Abstract

Abstract A computer memory checking system includes error detecting and correcting means which generate check digits stored with the words and which on read-out generate check digits from the word and compare them with the stored check digits. In the invention, the word, inciuding both data and check digits, is partitioned, and the portions are stored in separately- addressed random access memories (22, 24, 26). If a memory driver should fail, it will result in one of the random access memories being incorrectly addressed and delivering the wrong word portion. The error correcting circuits (54) will thereupon, in general, detect an uncorrectable multi-bit error. Means (notshown in Figure 1) are provided for storing syn- d rome bits indicative of the error, and for storing the address at which an error has occurred, and from these the failing drivers can be identified.

Inventors

  • 👤 Gary David Burns
  • 👤 Ferris Thomas Price

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 07:00
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 130 words
A computer memory checking system including error detecting and correcting means for generating check digits and storing them together with the data digits, for generating check digits on reading out the stored data, for comparing the digits so generated with the previously stored check digits, and thereby detecting and correcting single digit errors, and detecting multiple digit errors, characterised in that the data digits (WDO to WD7) and check digits (CO to C3, CT) of words to be stored are partitioned, each part is stored in a separate random access memory (22, 24, 26), and during each memory accessing cycle the address of a word is applied simultaneously to the memory drivers (28, 30, 32) for each of the random access memories to access all the portions of the word.
Claim 2
Dependent Claim 130 words
A computer memory checking system including error detecting and correcting means for generating check digits and storing them together with the data digits, for generating check digits on reading out the stored data, for comparing the digits so generated with the previously stored check digits, and thereby detecting and correcting single digit errors, and detecting multiple digit errors, characterised in that the data digits (WDO to WD7) and check digits (CO to C3, CT) of words to be stored are partitioned, each part is stored in a separate random access memory (22, 24, 26), and during each memory accessing cycle the address of a word is applied simultaneously to the memory drivers (28, 30, 32) for each of the random access memories to access all the portions of the word.
Claim 3
Dependent Claim 32 words
A computer memory checking system according to claim 1 further including means for generating (54C), and for storing (85), syndrome digits whose pattern indicates the types of error which have been detected.
Claim 4
Dependent Claim 30 words
A computer memory checking system according to claim 1 or claim 2 further including means (87) for recording the address from which a word containing an error has been accessed.

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