A data processing device for processing multiple-symbol data-words based on a symbol-correcting code and having multiple operating modes

Claim 1

A data processing device for the processing of data words which are composed of k = 2p-2 ≥ 2 data symbols by means of code words which are formed from the associated data words by means of an error-correcting code, said code words containing n=2p code symbols, all symbols consisting of m = 2s > 4 bits and forming part of a Galois field GF(2 m ) = {0, a , a ... a 2 m-2}, said device comprising a first input for a data word, first multiplier means for multiplying the data word by a generator matrix [G] consisting of nxk matrix element each of m bits in order to form a code word, processing means for processing the code word in order to form a processing result, and reconstruction means for reconstructing, using a parity check matrix [R] which is orthogonal to the generator matrix [G], the second data word associated with the processing result for output on a first output, characterized in that the reconstruction means comprise: a) second multiplier means (102) with a second input for receiving the processing result for multiplication by a parity check matrix [R] = [S]. [H]. [T] in order to form a number of at least (n-k) = 2t ≥ 2 syndrome symbols (SO, S1, S2, S3) on a second output, [S] being a non-singular matrix consisting of (mkxmk) bits, the matrix [H] comprising a first sub-matrix of kxk symbols in the form of an identity matrix and a second sub-matrix of kx (n-k) symbols whose determinant is not equal to 1 = a o , the absolute values modulo (2 m -1) of the differences between the exponents of the symbols written as powers of (a) being at least equal to (m) on each respective row and in each respective column of the matrix [H], while each (kxk) sub-matrix of [H] is non-singular, the matrix [T] consisting of (nmxnm) bits in nxn blocks which are arranged in rows and columns and each of which blocks consists of mxm bits, each row and each column of blocks comprising (n-1) blocks which consist exclusively of "0" bits, each row of bits and each column of bits containing exactly one "1" bit and for the remainder exclusively "0" bits; b) a mode register (110) which has a third input and a third output, a first state of the mode register controlling a "normal" mode for processing the code words as forming part of a code with a minimum Hamming-distance of three over the symbols or a minimum Hamming-distance of five over the bits, n respective second states of the mode register controlling an erasure operation for a code symbol uniquely associated with the respective second state in order to process the remaining code symbols as forming a code word of a code having a minimum distance of three over the bits; c) a data reconstruction device (104) with a fourth input (100) for receiving the processing result and a fifth input for receiving the syndrome symbols, and with a fourth output (Y32, Y31, Y30, Y21, Y20, Y10) for forming a reconstructed data word on the basis of associated sub-sets of k code symbols; d) a selection device (106) with a sixth input which is connected to the second output in order to receive the syndrome symbols and a seventh input which is connected to the third output in order to receive the state information from the mode register, and also with a sixth output which is connected to the third output and a seventh output for supplying, on the basis of the syndrome symbols and the state of the mode register, a selection signal for indicating the error-free code symbols and for supplying a set signal for the mode register; e) a gating device (112-122), with inputs which are connected to the fourth output and the seventh output for the selection of a corrected data word.