Patent EP0074805A2 successfully refreshed from Google Patents.
EP0074805A2
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EP
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Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
Assignee: Fujitsu Ltd
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Filing: 1982-09-09
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Granted: —
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Expires: 2002-09-09
Abstract
Abstract A semiconductor integrated circuit includes a conventional inner cell region (2) and an outer cell region (4). The outer cell region contains a plurality of outer cells (3;116,117) each comprising circuit elements (R 1 -R' 4 , Q 1 -Q' 9 ) for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Two or more adjacent outer cells (116,117) cooperate with each other and act as an independent circuit so as to form a macro-cell (118).
Inventors
- 👤 Tetsu Tanizawa
- 👤 Yoshiharu Mitono
- 👤 Hitoshi Omichi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
175 words
A semiconductor integrated circuit comprising a semiconductor substrate having a centre portion and a peripheral portion; first level and second level wiring layers (6-3,6-2) formed on the semiconductor substrate, the second level wiring layer being formed over the first level wiring layer; an inner cell region (2) located at the centre portion of the semiconductor substrate, the inner cell region comprising a plurality of inner cells (1) which are arranged in the form of arrays and are connected by the second wiring layer, each of the inner cells comprising a plurality of circuit elements interconnected by the first level wiring layer; and an outer cell region (4) located at the peripheral portion of the semiconductor substrate, the outer cell region comprising a plurality of outer cells (3) each of which comprises a plurality of circuit elements interconnected by the first level wiring layer, the plurality of circuit elements in the outer cell region being selectively connected with each other so that at least one of the outer cells has a different function from the others.
Claim 2
Dependent Claim
175 words
A semiconductor integrated circuit comprising a semiconductor substrate having a centre portion and a peripheral portion; first level and second level wiring layers (6-3,6-2) formed on the semiconductor substrate, the second level wiring layer being formed over the first level wiring layer; an inner cell region (2) located at the centre portion of the semiconductor substrate, the inner cell region comprising a plurality of inner cells (1) which are arranged in the form of arrays and are connected by the second wiring layer, each of the inner cells comprising a plurality of circuit elements interconnected by the first level wiring layer; and an outer cell region (4) located at the peripheral portion of the semiconductor substrate, the outer cell region comprising a plurality of outer cells (3) each of which comprises a plurality of circuit elements interconnected by the first level wiring layer, the plurality of circuit elements in the outer cell region being selectively connected with each other so that at least one of the outer cells has a different function from the others.
Claim 3
Dependent Claim
31 words
A circuit as claimed in Claim 1, wherein the first level wiring layer (6-3) selectively connects the plurality of circuit elements (41-49) which are included in the same outer cell (40).
Claim 4
Dependent Claim
27 words
A circuit as claimed in Claim 1, wherein the first level wiring layer selectively connects the plurality of circuit elements which are included in different outer cells.
Claim 5
Dependent Claim
39 words
A circuit as claimed in Claim 1, wherein at least one of the outer cells (40) has one input (5) for receiving an external input signal and also has a plurality of outputs (48,49) for producing output signals therefrom.
Claim 6
Dependent Claim
22 words
A circuit as claimed in Claim 4, wherein the output signals are all non-inverted signals with respect to the external input signal.
Claim 7
Dependent Claim
23 words
A circuit as claimed in Claim 4, wherein the output signals are all inverted signals with respect to the external input signal (5).
Claim 8
Dependent Claim
28 words
A circuit as claimed in Claim 4, wherein the output signals are a mixture of the inverted and non-inverted signals with respect to the external input signal (5).
Claim 9
Dependent Claim
46 words
A circuit as claimed in any preceding claim, wherein at least one set of two or more adjacent outer cells is defined as an independent circuit and the outer cells cooperate with each other therein, so as to form a macro-cell in the outer cell region.
Claim 10
Dependent Claim
46 words
A circuit as claimed in Claim 8, wherein the macro-cell includes gate means (134) for receiving a single external input signal and produces a plurality of inverted signals with respect to the single external input signal, the inverted signals being fed to the inner cell region.
Claim 11
Dependent Claim
46 words
A circuit as claimed in Claim 8, wherein the macro-cell includes gate means (135) for receiving a single external input signal and produces a plurality of non-inverted signals with respect to the single external input signal, the non-inverted signals being fed to the inner cell region.
Claim 12
Dependent Claim
49 words
A circuit as claimed in Claim 8, wherein the macro-cell includes gate means (123) for receiving a single external input signal and produces mixtures of inverted and non-inverted signals with respect to the single external input signal, the inverted and non-inverted signals being fed to the inner cell region.
Claim 13
Dependent Claim
47 words
A circuit as claimed in Claim 8, wherein the macro-cell includes a multi-input logic gate (133) cooperating with a plurality of external input signals (130-132), the logic gate operating as a known logic gate such as a multi-input NAND gate, multi-input AND gate, or multi-input latch gate.
References Cited (Backward Citations)
No citation records indexed.
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