Patent US562895A successfully refreshed from Google Patents.
Patent EP0073130A2 successfully refreshed from Google Patents.
EP0073130A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for manufacturing a mask type Read Only Memory
Assignee: Toshiba Corp
•
Filing: 1982-08-16
•
Granted: —
•
Expires: 2002-08-16
Abstract
Abstract A method of manufacturing a mask type read only memory having a plurality of MOS transistors is described, in which source and drain regions of certain of the MOS transistors are shorted in accordance with a requested program, after an interconnection wiring layer has been formed on the semiconductor substrate. The source and drain regions are interconnected by means of a channel (83) created by ion-implantation of a suitable impurity. The shorted MOS transistors are then covered by a protective layer (84), the contour of which indicates those MOS transistors which have been shorted.
Inventors
- 👤 Yoshihisa Shiotari
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 02:25
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
231 words
.A method of manufacturing a mask type Read Only Memory comprising the steps of: (a) selectively forming a first insulating layer having a thick portion (65) and a thin portion (67) for a field region and a gate insulating layer respectively, on a semiconductor substrate of a first conductivity type; (b) forming a polysilicon layer (68) on said insulating layer; (c) forming gate electrodes (69, 70) for MOS transistors by partially removing said polysilicon layer; (d) forming regions (74) of a second conductivity type in the substrate, to be source and drain regions of the MOS transistors; (e) forming a second insulating film (78) on the semiconductor substrate in which the MOS transistors are formed; (f) forming a contact hole (79) in the second insulating film (78) to the second conductivity type region of some of the MOS transistors,for allowing the formation of outer contact electrodes (80); (g) forming outer contact electrodes (80) and bonding pads (81); (h) connecting the source and drain regions of certain of the MOS transistors by means of a channel region (83) in accordance with a set program, by ion implantation of an impurity; (i) forming a protective film (84) on said bonding pads (81), the outer electrodes (80), and the MOS transistors; (j) removing said protective film (84) on the bonding pad (81); and (k) providing an outer electrode (86) to the bonding pad (81).
Claim 2
Dependent Claim
231 words
.A method of manufacturing a mask type Read Only Memory comprising the steps of: (a) selectively forming a first insulating layer having a thick portion (65) and a thin portion (67) for a field region and a gate insulating layer respectively, on a semiconductor substrate of a first conductivity type; (b) forming a polysilicon layer (68) on said insulating layer; (c) forming gate electrodes (69, 70) for MOS transistors by partially removing said polysilicon layer; (d) forming regions (74) of a second conductivity type in the substrate, to be source and drain regions of the MOS transistors; (e) forming a second insulating film (78) on the semiconductor substrate in which the MOS transistors are formed; (f) forming a contact hole (79) in the second insulating film (78) to the second conductivity type region of some of the MOS transistors,for allowing the formation of outer contact electrodes (80); (g) forming outer contact electrodes (80) and bonding pads (81); (h) connecting the source and drain regions of certain of the MOS transistors by means of a channel region (83) in accordance with a set program, by ion implantation of an impurity; (i) forming a protective film (84) on said bonding pads (81), the outer electrodes (80), and the MOS transistors; (j) removing said protective film (84) on the bonding pad (81); and (k) providing an outer electrode (86) to the bonding pad (81).
Claim 3
Dependent Claim
82 words
A method as claimed in claim 1, wherein step for forming the thick field insulating layer on the semiconductor substrate comprises the steps of: (a) forming a thermal oxide layer on the semiconductor substrate; (b) selectively forming a silicon nitride film on the thermal oxide layer; (c) forming a first thick insulating layer on the semiconductor substrate by oxidizing the semiconductor substrate using the silicon nitride film as a mask; and (d) removing said silicon nitride layer and the thermal oxide layer.
Claim 4
Dependent Claim
92 words
A method as claimed in claim 1 or claim 2, wherein the step of forming regions of a second conductivity type to the source and drain regions of the MOS transistors comprises the steps of: (a) forming gate insulating films in the MOS transistors by etching the thin insulating film (67) using the silicon gate as an etching mask; \ (b) forming an impurity source film on the semiconductor substrate, and (c) diffusing the impurities in the impurity source film into the semiconductor substrate so as to form source and drain regions.
Claim 5
Dependent Claim
61 words
A method as claimed in claim 1, 2 or 3, wherein the step of connecting the source regions and drain regions of said certain MOS transistors by means of a channel region includes the step of: selectively removing at least part of the second insulating film (78) and exposing the gate electrode, source and drain regions of said certain MOS transistors.
Claim 6
Dependent Claim
58 words
A method as claimed in claim 4, wherein said step for selectively removing the insulating film over the source regions and drain regions of said certain MOS transistors, includes the steps of: leaving a thin film (78A) of the second insulating film (78) oh the silicon gate electrodes (69) of at least some of said certain MOS transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.