Patent EP0072966A2 successfully refreshed from Google Patents.
EP0072966A2
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EP
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Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
Assignee: International Business Machines Corp
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Filing: 1982-08-10
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Granted: —
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Expires: 2002-08-10
Abstract
Abstract An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.
Inventors
- 👤 Richard Carleton Joy
- 👤 Bernard Michael Kemlage
- 👤 John Lester Mauer Iv
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:57
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/041; H10W10/10; H10W10/13; H10W10/40; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
109 words
Integrated circuit structure having substrate contacts comprising: a monocrystalline silicon body (2); a pattern of dielectric isolation surrounding regions of said monocrystalline silicon in body (2); said pattern including a recessed dielectric portion (14) at the surface of the integrated circuit and a deep portion (30) which extends through recessed portion (14) and extends further into monocrystalline silicon body (2) than recessed portion (14); and a doped polycrystalline silicon substrate contact (30) located within the deep portion of said pattern of isolation and extending from the surface of said pattern of isolation down to the bottom of the deep portion where said contact electrically connects to silicon body (2).
Claim 2
Dependent Claim
109 words
Integrated circuit structure having substrate contacts comprising: a monocrystalline silicon body (2); a pattern of dielectric isolation surrounding regions of said monocrystalline silicon in body (2); said pattern including a recessed dielectric portion (14) at the surface of the integrated circuit and a deep portion (30) which extends through recessed portion (14) and extends further into monocrystalline silicon body (2) than recessed portion (14); and a doped polycrystalline silicon substrate contact (30) located within the deep portion of said pattern of isolation and extending from the surface of said pattern of isolation down to the bottom of the deep portion where said contact electrically connects to silicon body (2).
Claim 3
Dependent Claim
35 words
Integrated circuit structure of claim 1 characterized in that recessed dielectric portion (14) is greater than about 1.5 pm in width and less than 1.5 pm in depth, and composed of thermally grown silicon dioxide.
Claim 4
Dependent Claim
46 words
Integrated circuit structure of claim 1 characterized in that the deep portion (30) is less than 5 µm in width and 6 µm in depth and has substantially vertical sidewalls (28) composed of silicon dioxide with polycrystalline silicon contained within sidewalls (28) of said deep portion.
Claim 5
Dependent Claim
29 words
Integrated circuit structure of claim 1 characterized in that a bipolar transistor or a field effect transistor is located in at least some of said regions of monocrystalline silicon.
Claim 6
Dependent Claim
21 words
Bipolar integrated circuit structure of claim 4 characterized in that subcollector region (6) overlaps the substrate (2) and epitaxial layer (4).
Claim 7
Dependent Claim
28 words
Bipolar integrated circuit structure of claim 4 characterized in that the bipolar transistor is an NPN, the doped polycrystalline silicon is P+ and the silicon substrate is P.
Claim 8
Dependent Claim
216 words
Method for forming a recessed isolation structure for an integrated circuit structure having substrate contacts comprising: forming a first masking layer (8, 10, 12) over a major surface of a monocrystalline silicon substrate (2, 4); opening a pattern in first masking layer (8, 10, 12) to the major surface wherein isolation structure (14) is desired; forming the recessed dielectric portion (14) of the dielectric isolation by reactive ion etching, and oxidizing the exposed monocrystalline substrate (4); removing first masking layer (8, 10, 12); forming a second masking layer (18, 20, 22) over the major surface; opening a pattern in second masking layer (18, 20, 22) in the recessed isolation structure (14) wherein said substrate contacts are to be formed; forming through said opening a pattern of trenches (30) by reactive ion etching having substantially vertical sidewalls through the recessed isolation structure (14) and into the monocrystalline silicon (2, 4, 6) thereunder; forming an insulating layer (28) upon the surfaces of trenches (30); removing insulating layer (28) from the bottom surfaces of trenches (30); depositing a layer of polycrystalline silicon over substrate (2, 4, 6) to fill trenches (30); and planarizing the major surface of substrate (2, 4, 6) by a reactive ion etching process which substantially removes the layer of polycrystalline silicon except from said trenches.
Claim 9
Dependent Claim
216 words
Method for forming a recessed isolation structure for an integrated circuit structure having substrate contacts comprising: forming a first masking layer (8, 10, 12) over a major surface of a monocrystalline silicon substrate (2, 4); opening a pattern in first masking layer (8, 10, 12) to the major surface wherein isolation structure (14) is desired; forming the recessed dielectric portion (14) of the dielectric isolation by reactive ion etching, and oxidizing the exposed monocrystalline substrate (4); removing first masking layer (8, 10, 12); forming a second masking layer (18, 20, 22) over the major surface; opening a pattern in second masking layer (18, 20, 22) in the recessed isolation structure (14) wherein said substrate contacts are to be formed; forming through said opening a pattern of trenches (30) by reactive ion etching having substantially vertical sidewalls through the recessed isolation structure (14) and into the monocrystalline silicon (2, 4, 6) thereunder; forming an insulating layer (28) upon the surfaces of trenches (30); removing insulating layer (28) from the bottom surfaces of trenches (30); depositing a layer of polycrystalline silicon over substrate (2, 4, 6) to fill trenches (30); and planarizing the major surface of substrate (2, 4, 6) by a reactive ion etching process which substantially removes the layer of polycrystalline silicon except from said trenches.
Claim 10
Dependent Claim
46 words
Method of claim 7 characterized in that prior to the oxidizing the exposed substrate is etched so that when said oxidizing is completed the top surface of the formed silicon dioxide (14, 26) will be substantially planar with the major surface of said silicon substrates (4).
Claim 11
Dependent Claim
17 words
Method of claim 7 characterized in that the first masking layer (8) is composed of silicon oxynitride.
Claim 12
Dependent Claim
35 words
Method of claim 7 characterized in that the second masking layer (18, 20, 22) is removed and the desired active and passive devices are formed in said monocrystalline silicon substrate between said recessed isolation structure.
Claim 13
Dependent Claim
46 words
Method of claim 7 characterized in that for a bipolar integrated circuit structure the monocrystalline substrate includes a base silicon layer (2) and an epitaxial layer (4) thereover and that there is provided a subcollector layer (6) overlaping base silicon layer (2) and epitaxial layer (4).
Claim 14
Dependent Claim
31 words
Method of claim 7 characterized in that insulating layer (28) on the surfaces of the trenches is silicon dioxide and formed by thermal oxidation and chemical vapor deposition of silicon dioxide.
Claim 15
Dependent Claim
26 words
Method of claim 12 characterized in that the insulating layer (28) is removed from the bottom surfaces by anisotropic etching using a reactive ion etching process.
References Cited (Backward Citations)
No citation records indexed.
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