Patent EP0071276A2 successfully refreshed from Google Patents.
EP0071276A2
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EP
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High switching speed semiconductor device containing graded killer impurity
Assignee: Hitachi Ltd
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Filing: 1982-07-30
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Granted: —
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Expires: 2002-07-30
Abstract
Abstract A semiconductor device for controlling a current comprising a pn junction (5, 15, 16) formed of a high resistivity region (1. 11) and a relatively low resistivity region (3, 12, 13), graded distribution of dislocation density which is formed in the high resistivity region and decreases with an increase in distance from the pn junction, and graded distribution of lifetime killer concentration which is formed in the high resistivity region and decreases with an increase in distance from the pn junction in correspondence with the graded distribution of dislocation density.
Inventors
- 👤 Kensuke Suzuki
- 👤 Mitsuyuki Matsuzaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 11:29
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D18/00; H10D18/241; H10D8/00; H10D8/422; H10P; H10P36/00; H10P36/03; H10P95/00; H10P95/40; H10P95/402
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
114 words
A semiconductor device including at least one pn junction across which a current is allowed to flow, comprising: a first semiconductor region (1, 11) of a first conductivity type having a high resistivity; a second semiconductor region (3, 12, 13) of a second conductivity type opposite to said first conductivity type, having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to said first semiconductor region to form one of said at least one p n junction therebetween; and a graded distribution of lifetime killer formed in said first semiconductor region and having a killer concentration distribution which decreases with an increase in distance from said one pn junction.
Claim 2
Dependent Claim
114 words
A semiconductor device including at least one pn junction across which a current is allowed to flow, comprising: a first semiconductor region (1, 11) of a first conductivity type having a high resistivity; a second semiconductor region (3, 12, 13) of a second conductivity type opposite to said first conductivity type, having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to said first semiconductor region to form one of said at least one p n junction therebetween; and a graded distribution of lifetime killer formed in said first semiconductor region and having a killer concentration distribution which decreases with an increase in distance from said one pn junction.
Claim 3
Dependent Claim
45 words
+ A semiconductor device according to claim 1, further comprising: graded distribution of dislocation formed in said first semiconductor region for enhancing doping of said lifetime killer and having a dislocation density distribution which decreases with an increase in distance from said one pn junction.
Claim 4
Dependent Claim
79 words
A semiconductor device according to claim 2, further comprising: a third semiconductor region (2) of said first conductivity type having a resistivity lower than that of said first semiconductor region and disposed adjacent tc an end of said first semiconductor region opposite to said second semiconductor region; and said distributions of the lifetime killer concentration and the dislocation density decreasing with an increase in distance from said one pn junction in substantially main part of said first semiconductor region.
Claim 5
Dependent Claim
89 words
A semiconductor device according to claim 2, further comprising: a fourth semiconductor region (13, 12) of said second conductivity type having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to an end of said first semiconductor region opposite to said second semiconductor region to form another of said at least one pn junction therebetween; and said distributions of dislocation density and lifetime killer concentration decreasing in portions from said one and another pn junctions toward a central portion of the first semiconductor region.
Claim 6
Dependent Claim
37 words
A semiconductor device according to claim 3, wherein said first conductivity type is n type and said third semiconductor region is doped with phosphorus of a concentration higher than the impurity concentration of said second semiconductor region.
Claim 7
Dependent Claim
36 words
A semiconductor device according to any one of claims 1 to 5, wherein the impurity concentration of said second semiconductor region is at least two orders of magnitude higher than that of said first semiconductor region.
Claim 8
Independent Claim
61 words
A method of manufacturing a semiconductor device including at least one pn junction across which a current is allowed to flow, comprising the steps of: -forming a strained surface layer in a semiconductor body; subjecting said semiconductor body to a heat treatment and thereby generating and growing dislocation from said strained surface layer; and doping lifetime killer in said semiconductor body.
Claim 9
Independent Claim
61 words
A method of manufacturing a semiconductor device including at least one pn junction across which a current is allowed to flow, comprising the steps of: -forming a strained surface layer in a semiconductor body; subjecting said semiconductor body to a heat treatment and thereby generating and growing dislocation from said strained surface layer; and doping lifetime killer in said semiconductor body.
Claim 10
Dependent Claim
30 words
A method of manufacturing a semiconductor device according to claim 7, wherein said step of forming a strained surface layer includes removal of a surface layer of said semiconductor body.
Claim 11
Dependent Claim
26 words
A method of manufacturing a semiconductor device according to claim 7, wherein said step of subjecting the semiconductor body to a heat treatment includes diffusing impurity.
Claim 12
Independent Claim
129 words
A method of manufacturing a high switching speed diode comprising the steps of: preparing a high resistivity silicon wafer of one conductivity type having a pair of opposed main surfaces; diffusing impurity of said one conductivity type in said silicon wafer; removing a diffused surface layer of said silicon wafer to expose a high resistivity region and forming a strained surface layer at the exposed high resistivity region; diffusing impurity of the other conductivity type opposite to said one conductivity type in the exposed high resistivity region and forming a graded dislocation density which decreases from said strained surface layer toward the main surface on the opposite side; and diffusing lifetime killer in said silicon wafer to establish a graded lifetime killer concentration corresponding to said graded dislocation density.
Claim 13
Independent Claim
129 words
A method of manufacturing a high switching speed diode comprising the steps of: preparing a high resistivity silicon wafer of one conductivity type having a pair of opposed main surfaces; diffusing impurity of said one conductivity type in said silicon wafer; removing a diffused surface layer of said silicon wafer to expose a high resistivity region and forming a strained surface layer at the exposed high resistivity region; diffusing impurity of the other conductivity type opposite to said one conductivity type in the exposed high resistivity region and forming a graded dislocation density which decreases from said strained surface layer toward the main surface on the opposite side; and diffusing lifetime killer in said silicon wafer to establish a graded lifetime killer concentration corresponding to said graded dislocation density.
References Cited (Backward Citations)
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