Patent EP0071010A2 successfully refreshed from Google Patents.
EP0071010A2
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Method for planarizing an integrated circuit structure
Assignee: International Business Machines Corp
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Filing: 1982-06-15
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Granted: —
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Expires: 2002-06-15
Abstract
Abstract A method is given for planarizing an integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having device elements (14, 16, 20) formed therein but before interconnection metallurgy (42, 44, 46) has been formed on the principal surface of the product. A glass layer (40) is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200°C. The structure is heated to cause the flow of glass (40) on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass (40) down to the device elements (14, 16, 20) of the integrated circuit. The interconnection metallurgy (42,44,46) is formed over the surface of glass (40) and through the openings of the glass to interconnect the device elements (14, 16, 20) of the integrated circuit. The glass (40) may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods.
Inventors
- 👤 William Aaron Pliskin
- 👤 Jacob Riseman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 21:51
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6329; H10P14/6342; H10P14/65; H10P14/6502; H10P14/6506; H10P95/00; H10P95/06; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10W74/40; H10W74/43; H10P14/6923
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
159 words
Method for planarizing an integrated circuit structure having device elements (14, 16, 20; 58, 60, 66) formed therein and prior to forming metallurgy (42, 44, 46; 72, 74, 76) on a principal surface of said structure, characterized in that a glass layer (40, 70) having a thermal coefficient of expansion that approximates that of silicon and a softening temperature of less than about 1200°C is non-conformally deposited onto said surface; that the structure is heated to cause the flow of glass (40, 70) on said surface to fill in the irregularities therein and to planarize said surface; that openings are formed through glass (40, 70) down to the device elements ( 14, 16, 20; 58, 60, 66) of the integrated circuit; and that an interconnection metallurgy (42, 44, 46; 72, 74, 76) is formed over and through said openings in glass (40, 70) to interconnect the device elements ( 14, 16, 20; 58, 60, 66) of the integrated circuit.
Claim 2
Dependent Claim
159 words
Method for planarizing an integrated circuit structure having device elements (14, 16, 20; 58, 60, 66) formed therein and prior to forming metallurgy (42, 44, 46; 72, 74, 76) on a principal surface of said structure, characterized in that a glass layer (40, 70) having a thermal coefficient of expansion that approximates that of silicon and a softening temperature of less than about 1200°C is non-conformally deposited onto said surface; that the structure is heated to cause the flow of glass (40, 70) on said surface to fill in the irregularities therein and to planarize said surface; that openings are formed through glass (40, 70) down to the device elements ( 14, 16, 20; 58, 60, 66) of the integrated circuit; and that an interconnection metallurgy (42, 44, 46; 72, 74, 76) is formed over and through said openings in glass (40, 70) to interconnect the device elements ( 14, 16, 20; 58, 60, 66) of the integrated circuit.
Claim 3
Dependent Claim
27 words
Method of claim 1, characterized in that a silicon dioxide layer (22, 32, 31; 54, 62, 641 is formed substantially under all of glass layer (40, 70).
Claim 4
Dependent Claim
33 words
Method of claim 2, characterized in that when there is a significant sodium content in glass (40, 70) a silicon nitride layer (23) is intermediate to silicon dioxide (22) and glass layer (401.
Claim 5
Dependent Claim
38 words
Method of claim 1, characterized in that glass (40, 70) is formed by a sedimentation process which involves spray coating of glass particles, centrifuging or spin-on of a coating of glass particles upon said surfaces of said substrate.
Claim 6
Dependent Claim
16 words
Method of claim 1, characterized in that glass (40, 70) is formed by a sputtering process.
Claim 7
Dependent Claim
16 words
Method of claim 1, characterized in that glass (40, 70) is formed by an evaporation process.
Claim 8
Dependent Claim
24 words
Method of claim 1, characterized in that the heating step raises the temperatures of said structure to less than about 1000°C to cause flow.
Claim 9
Dependent Claim
29 words
Method of claim 1, characterized in that a glass is used which has a thermal coefficient of expansion between about 20 to 60 x 10 -7 per degree centrigrade.
Claim 10
Dependent Claim
29 words
Method of claims 1 and 8, characterized in that the glass is selected from the group of lead borosilicate glass, calcium alumino borosilicate glass, β-spodumene glass-ceramic, and cordierite glass-ceramic.
Claim 11
Dependent Claim
16 words
Method of claims 1 and 8, characterized in that glass (40, 70) is substantially sodium free.
Claim 12
Dependent Claim
99 words
Substantially planarized integrated circuit structure comprising: a non-planar, irregular surfaced integrated circuit structure having a silicon dioxide layer (22, 32, 31; 54, 62, 64) covering its upper surface; a substantially planar glass layer (40, 70) covering and filling said non-planar structure; said glass layer (40, 70) having a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200°C; and interconnection metallurgy (42, 44, 46; 72, 74, 76) over and through said glass layer (40, 70) connecting to the device elements (14, 16, 20; 58, 60, 66) of said integrated circuit.
Claim 13
Dependent Claim
99 words
Substantially planarized integrated circuit structure comprising: a non-planar, irregular surfaced integrated circuit structure having a silicon dioxide layer (22, 32, 31; 54, 62, 64) covering its upper surface; a substantially planar glass layer (40, 70) covering and filling said non-planar structure; said glass layer (40, 70) having a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200°C; and interconnection metallurgy (42, 44, 46; 72, 74, 76) over and through said glass layer (40, 70) connecting to the device elements (14, 16, 20; 58, 60, 66) of said integrated circuit.
Claim 14
Dependent Claim
35 words
Integrated circuit structure of claim 11, wherein further and alternative layers of insulating layer and connecting metallurgy layers are positioned over said interconnecting metallurgy for further interconnecting the device elements to said integrated circuit structure.
Claim 15
Dependent Claim
18 words
Integrated circuit of claim 11, wherein said integrated circuit includes a substantial number of bipolar transistor devices therein.
Claim 16
Dependent Claim
19 words
The integrated circuit of claim 11, wherein said integrated circuit includes a substantial number of field effect devices therein.
References Cited (Backward Citations)
No citation records indexed.
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