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EP0070744A2
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Insulated gate field effect transistor
Assignee: Hitachi Ltd
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Filing: 1982-07-22
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Granted: —
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Expires: 2002-07-22
Abstract
Abstract An insulated gate field effect transistor has a well region (42) formed in a semiconductor substrate (41) of different conductivity type. The well region (42) has an opening in it so that a part of the substrate (47) extends within it. Source and drain regions (43, 44) are formed in the well region (42) on opposite sides of the opening, with the same conductivity type as the substrate (41). An insulated layer (45) is formed on the surface of the substrate between the source and drain regions (43, 44) and a gate electrode (46) is formed on the insulating layer (45). A potential is applied to the gate electrode (46) to reverse-bias the substrate-well junction and a depletion layer (48) is formed which includes the part of the substrate (41) between the source and drain regions (43, 44). This enables the transistor to have a small body effect, so that it may be operated with a constant current character.
Inventors
- 👤 Yoshio Sakai
- 👤 Tsuneo Funabashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:40
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/60; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0156; H10D84/0158; H10D84/0165; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
130 words
An insulated gate field effect transistor comprising a substrate (41), source and drain regions (43,44) of a first conductivity type extending from the surface of the substrate (41), an insulating layer (45) on the surface of the substrate (41) extending between the source and drain regions (43,44), and a gate electrode (46) on the insulating layer (45), the substrate (41) having a part lying between the source and drain regions (43,44); characterised in that: the substrate (41) is of the first conductivity type, and a well region (42) of second conductivity type is provided in the substrate (41), the well region (42) extending from the surface of the substrate (41) and contacting the source and drain regions (43,44) at a part thereof spaced from the surface of the substrate (41).
Claim 2
Dependent Claim
130 words
An insulated gate field effect transistor comprising a substrate (41), source and drain regions (43,44) of a first conductivity type extending from the surface of the substrate (41), an insulating layer (45) on the surface of the substrate (41) extending between the source and drain regions (43,44), and a gate electrode (46) on the insulating layer (45), the substrate (41) having a part lying between the source and drain regions (43,44); characterised in that: the substrate (41) is of the first conductivity type, and a well region (42) of second conductivity type is provided in the substrate (41), the well region (42) extending from the surface of the substrate (41) and contacting the source and drain regions (43,44) at a part thereof spaced from the surface of the substrate (41).
Claim 3
Dependent Claim
42 words
An insulated gate field effect transistor according to claim 1, wherein the well region (42) contacts parts of the source and drain regions (43,44) spaced from the parts of those regifns (43,44) between which the part (47) of the substrate (41) extends.
Claim 4
Dependent Claim
26 words
An insulated gate field effect transistor according to claim 1, wherein the well region (42) encloses the source and drain regions (43,44) within the substrate (41).
Claim 5
Dependent Claim
32 words
An insulated gate field effect transistor according to any one of claims 1 to 3, wherein said well region (42) has an impurity concentration higher than that of said semiconductor substrate (41).
Claim 6
Dependent Claim
41 words
An insulated gate field effect transistor according to any one of the preceding claims wherein an impurity layer of said second conductivity type is provided between the insulating layer and the part of the substrate between the source and drain regions.
Claim 7
Dependent Claim
22 words
An insulated gate field effect transistor according to claim 5, wherein the impurity layer has a thickness of not more than 0.5µm.
Claim 8
Dependent Claim
41 words
An insulated gate field effect transistor according to any one of the preceding claims, having bias means to set potentials of the substrate and the well region so that a junction between the substrate and the well region may be reverse-biased.
Claim 9
Dependent Claim
31 words
An insulated gate field effect transistor according to claim 7, wherein the bias means forms a depletion layer in all the part of the substrate between the source and drain regions.
Claim 10
Dependent Claim
34 words
An insulated gate field effect transistor according to claim 7, wherein the bias means forms a depletion layer in the peripheral regions of the part of the substrate between the source and drain regions.
Claim 11
Dependent Claim
25 words
An insulated gate field effect transistor according to any one of the preceding claims, provided in the same semiconductor chip with a complementary MOS circuit.
Claim 12
Dependent Claim
25 words
An insulated gate field effect transistor according to any one of the preceding claims, wherein said gate electrode and said source region are electrically connected.
Claim 13
Dependent Claim
51 words
An insulated gate field effect transistor according to claim 11, wherein said drain region is connected to a power source, said transistor is driven by a logic network connected to a common end of the source region and the gate electrode, and said common end is used as an output terminal.
References Cited (Backward Citations)
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