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EP0070387A2
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Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3
Assignee: International Business Machines Corp
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Filing: 1982-06-08
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Granted: —
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Expires: 2002-06-08
Abstract
Abstract An encoder for producing a run length limited code useful in magnetic recording channels producing sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 2 bits of unconstrained data (s) into 3 bits of constrained date (y). The encoder comprises a fairly simple logic network (20) and is a finite state machine whose internal state description requires 3 bits (x). It possesses the attractive feature of certain reset data blocks which reset it to a fixed state. The error propagation due to a random error is 5 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
Inventors
- 👤 Roy Lee Adler
- 👤 Martin Hassner
- 👤 John Peter Moussouris
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 10:33
CPC Classifications
G; G06; G06T; G06T9/00; G06T9/005; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
86 words
A method for encoding a series of unconstrained binary input symbols into a run length limited (1,7) code having a 2/3 rate which comprises consecutively entering two new input symbols (S) into a tree coding network and simultaneously entering three state bits (X) which were produced by the encoder during the immediately preceding encoding operation into the same encoding network and producing three channel output bits (Y') obeying said (1,7) encoding rules and three next state bits (X') for use in the next succeeding coding operation.
Claim 2
Independent Claim
86 words
A method for encoding a series of unconstrained binary input symbols into a run length limited (1,7) code having a 2/3 rate which comprises consecutively entering two new input symbols (S) into a tree coding network and simultaneously entering three state bits (X) which were produced by the encoder during the immediately preceding encoding operation into the same encoding network and producing three channel output bits (Y') obeying said (1,7) encoding rules and three next state bits (X') for use in the next succeeding coding operation.
Claim 3
Dependent Claim
36 words
A method for encoding as set forth in claim 1 including mapping the two input bits (S) into said three channel bits (Y') and said three next state bits (X') according to the following mapping table:
Claim 4
Dependent Claim
50 words
A method for encoding as set forth in claim 1 or 2, including inserting a predetermined data input configuration into the input code stream to force the next state bits (X') to assume a predetermined pattern whereby a predetermined channel code configuration is produced which is adapted for control use.
Claim 5
Dependent Claim
122 words
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment having a minimum of 1 and a maximum of seven 0's between adjacent 1's and a coding rate 2/3, said encoder comprising means for receiving as an input vector for a given encoding operation two new message bits (S) and a three bit state vector (X) derived from the immediately preceding encoding operation, logic circuit means for producing a channel vector (Y') obeying said RLL coding rules and a next state vector (X') which becomes the state vector (X) for use in the next encoding operation wherein the vectors Y' and X' are functions of all five input bits to the encoder logic circuit means.
Claim 6
Dependent Claim
122 words
An encoder for producing a run length limited (RLL) code for use in a structurally constrained environment having a minimum of 1 and a maximum of seven 0's between adjacent 1's and a coding rate 2/3, said encoder comprising means for receiving as an input vector for a given encoding operation two new message bits (S) and a three bit state vector (X) derived from the immediately preceding encoding operation, logic circuit means for producing a channel vector (Y') obeying said RLL coding rules and a next state vector (X') which becomes the state vector (X) for use in the next encoding operation wherein the vectors Y' and X' are functions of all five input bits to the encoder logic circuit means.
Claim 7
Dependent Claim
21 words
An encoder as set forth in claim 4 wherein said logic circuit means comprises a maximum of two functional logic levels.
Claim 8
Dependent Claim
40 words
An encoder as set forth in Claim 5 wherein said logic circuit means performs a mapping function to map the two input vectors S and X into the two output vectors Y' and X' according to the mapping function table:
References Cited (Backward Citations)
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