Patent EP0070380A2 successfully refreshed from Google Patents.
EP0070380A2
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EP
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Discrete thin film capacitor
Assignee: International Business Machines Corp
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Filing: 1982-06-02
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Granted: —
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Expires: 2002-06-02
Abstract
Abstract A decoupling thin film capacitor for mounting on an integrate circuit multi-layer ceramic. A bottom layer metallurgy (2) is evaporated or sputtered onto a carrier (1). A high dielectric layer (3) is deposited, followed by a top metallurgy (4) and an isolating layer (5). Via holes are etched to respective electrode layers, ball limiting metallurgy (6) deposited thereon followed by solder balls (7). The capacitor can be mounted onto a ceramic substrate face down in contact with a compatible footprint.
Inventors
- 👤 William E. Dougherty
- 👤 Irving Feinberg
- 👤 James N. Humenik
- 👤 Alan Platt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 10:38
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/002; H01G4/228; H01G2/00; H01G2/02; H01G2/06; H01G2/065; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
134 words
A chip capacitor comprising a bottom conductive layer (2) having sequentially coated thereon a dielectric layer (3), a top conductive layer (4), and an insulating layer (5); first and second via holes, of which said first via holes (Fig. 4) extend through said insulating layer (5) to expose said top conductive layer (4), and said second via holes (8) extend through said insulating (5), top conductive (4), and dielectric layers (3) to expose said bottom conductive layer (2), whereby said insulating layer preferably extends about the side walls of said top conductive layer (4) in said second via holes (8) to insulate said top conductive layer, and isolated solder mounds (7) selectively deposited on said insulating layer (5) over and in said via holes in electric contact with an exposed conductive layer (2;4) therein.
Claim 2
Dependent Claim
134 words
A chip capacitor comprising a bottom conductive layer (2) having sequentially coated thereon a dielectric layer (3), a top conductive layer (4), and an insulating layer (5); first and second via holes, of which said first via holes (Fig. 4) extend through said insulating layer (5) to expose said top conductive layer (4), and said second via holes (8) extend through said insulating (5), top conductive (4), and dielectric layers (3) to expose said bottom conductive layer (2), whereby said insulating layer preferably extends about the side walls of said top conductive layer (4) in said second via holes (8) to insulate said top conductive layer, and isolated solder mounds (7) selectively deposited on said insulating layer (5) over and in said via holes in electric contact with an exposed conductive layer (2;4) therein.
Claim 3
Dependent Claim
24 words
The chip capacitor of claim 1, further comprising a carrier substrate (1) for mounting said bottom conductive layer (2), said carrier being preferably silicon.
Claim 4
Dependent Claim
20 words
The chip capacitor of claims 1 or 2, wherein said capacitor is mounted on a support surface for semiconductor chips.
Claim 5
Dependent Claim
22 words
The capacitor of claim 1, further comprising contact promoting metallurgy (6) between each joined solder mound and an exposed conductive layer portion.
Claim 6
Dependent Claim
43 words
The capacitor of claim 4, wherein said bottom conductive layer (2) comprises Ti/W or Ta; said dielectric layer (3) comprises lead lanthanum zirconate titanate (PLZT), said top conductive layer (4) comprises Al or Cu, and/or said insulating layer (5) comprises Si0 2 .
Claim 7
Independent Claim
124 words
A method of making a discrete thin film capacitor comprising the steps of: successively depositing a bottom conductive layer (2), a dielectric layer (3) and a top conductive layer (4) on a carrier substrate (1), etching a portion of said top conductive layer (4) and said dielectric layer (3) to expose said bottom conductive layer (2), depositing a layer of passivation material (5) over said etched portion (8) and unetched areas, etching said insulating material (5) to expose said top conductive layer (4) at selected portions of said unetched area and to isolate said top conductive layer (4) from said bottom conductive layer (2) while exposing said bottom conductive layer (2), and depositing a layer of ball limiting metallurgy (6) over all exposed portions.
Claim 8
Independent Claim
124 words
A method of making a discrete thin film capacitor comprising the steps of: successively depositing a bottom conductive layer (2), a dielectric layer (3) and a top conductive layer (4) on a carrier substrate (1), etching a portion of said top conductive layer (4) and said dielectric layer (3) to expose said bottom conductive layer (2), depositing a layer of passivation material (5) over said etched portion (8) and unetched areas, etching said insulating material (5) to expose said top conductive layer (4) at selected portions of said unetched area and to isolate said top conductive layer (4) from said bottom conductive layer (2) while exposing said bottom conductive layer (2), and depositing a layer of ball limiting metallurgy (6) over all exposed portions.
Claim 9
Dependent Claim
44 words
The method of claim 6, wherein the step of depositing a bottom layer (2) and a dielectric layer (3) comprises sputtering or evaporating said bottom layer (2) directly on said carrier (1) and sputtering said dielectric layer (3) directly on said bottom layer (2).
Claim 10
Dependent Claim
27 words
The method of claim 6, further comprising the step of evaporating Al or Cu directly onto the dielectric layer (3) to form said top conductive layer (4).
Claim 11
Dependent Claim
51 words
The method of claim 6, further comprising the steps of placing a solder ball (7) over selected areas of said ball limiting metallurgy (6) to define selective contacts with said top and bottom conductive layers (2; 4) and cutting the resulting capacitor to size for mounting on an integrated circuit laminate.
Claim 12
Dependent Claim
13 words
The method of claim 6, wherein said insulating material is SiO 2 .
References Cited (Backward Citations)
No citation records indexed.
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