Patent EP0068358A2 successfully refreshed from Google Patents.
EP0068358A2
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Apparatus for parallel processing of local image data
Assignee: Hitachi Ltd
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Filing: 1982-06-18
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Granted: —
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Expires: 2002-06-18
Abstract
Abstract A apparatus for parallelly processing image data from a local image data source, in which m rows x n columns image data are processed by simultaneously processing n image data for each of the m rows (m and n being integers). The apparatus comprises a member (31, 71) for serially receiving image data, a memory section (21, 79, 87) having processing parameter data stored therein, a plurality of juxtaposed processor stages (22, 76, 83, 88) coupled to the memory section and arranged to be simultaneously supplied with sequentially shifted image data to thereby simultaneously produce processing results from the supplied image data and the processing parameter data, and an output section (23, 77, 84 to 86, 89, 91, 92) for receiving the outputs of the processor stages and delivering a processed output. The processing apparatus is suitable to implement in an IC form.
Inventors
- 👤 Yoshiki Kobayashi
- 👤 Tadashi Fukushima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 08:56
CPC Classifications
G; G06; G06T; G06T5/00; G06T5/20
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
114 words
An apparatus for parallel processing of local image data from a local image data source, comprising: means (31, 71) for receiving local image data; memory means (21, 79, 87) having processing parameter data stored therein; a plurality of juxtaposed processor stages (22, 76, 83, 88) coupled to said memory means; means (41, 42, 52, 62, 75) for simultaneously supplying via said receiving means sequentially shifted image data to said juxtaposed processor stages to thereby simultaneously produce processing resuls from said supplied image data and said processing parameter data from said memory means; and means (23, 77, 78, 84 to 86, 89, 91, 92) coupled to each of said processor stages for processing their outputs.
Claim 2
Independent Claim
114 words
An apparatus for parallel processing of local image data from a local image data source, comprising: means (31, 71) for receiving local image data; memory means (21, 79, 87) having processing parameter data stored therein; a plurality of juxtaposed processor stages (22, 76, 83, 88) coupled to said memory means; means (41, 42, 52, 62, 75) for simultaneously supplying via said receiving means sequentially shifted image data to said juxtaposed processor stages to thereby simultaneously produce processing resuls from said supplied image data and said processing parameter data from said memory means; and means (23, 77, 78, 84 to 86, 89, 91, 92) coupled to each of said processor stages for processing their outputs.
Claim 3
Independent Claim
141 words
An apparatus for parallel processing of image data from a local image data source, comprising: means (31, 71) for receiving local image data; a plurality of data memories (21) having weight data stored therein and serving to store said image data serially introduced via said receiving means; a plurality of processor stages (22) each including a multiplier and provided one for each of said data memories for producing products of said image data and said weight data, said data memories and the corresponding processor stages constituting juxtaposed processor units (20-1 to 20-4) so that said serially introduced image data are sequentially shifted between adjacent ones of said juxtaposed processor units renewed and said products are simultaneously produced each time a shift of said image data is effected; and means (23) for summing the outputs of said multipliers in said processor stages.
Claim 4
Independent Claim
141 words
An apparatus for parallel processing of image data from a local image data source, comprising: means (31, 71) for receiving local image data; a plurality of data memories (21) having weight data stored therein and serving to store said image data serially introduced via said receiving means; a plurality of processor stages (22) each including a multiplier and provided one for each of said data memories for producing products of said image data and said weight data, said data memories and the corresponding processor stages constituting juxtaposed processor units (20-1 to 20-4) so that said serially introduced image data are sequentially shifted between adjacent ones of said juxtaposed processor units renewed and said products are simultaneously produced each time a shift of said image data is effected; and means (23) for summing the outputs of said multipliers in said processor stages.
Claim 5
Dependent Claim
42 words
An apparatus according to Claim 2, in which each of said data memories (21) includes a two-port RAM (40), one port for delivering a renewed image data and a weight data, the other port for delivering an image data to be shifted.
Claim 6
Dependent Claim
84 words
An apparatus according to Claim 2, in which each of said data memories (21) includes a shift register (50) and a one-port RAM (51), the arrangement being such that the renewed image data is supplied, via said shift register, to said RAM for storage and to the multiplier in the corresponding processor stage for production of said product and that the former image data stored in said RAM is shifted, via said shift register, to the data memory in the succeeding adjacent processor units.
Claim 7
Dependent Claim
106 words
An apparatus according to Claim 2, in which each of said data memories (21) includes a shift register (60) for storing predetermined number of shifted image data and a one-port RA M (61) having said weight data stored therein, the arrangement being such that the renewed image data is supplied from the shift register in the preceding adjacent processor unit to the first-mentioned shift register for storage and to the multiplier in the corresponding processor stage for production of said product and that the former image data stored in the first-mentioned shift register is shifted therefrom to the data memory in the succeeding adjaced processor unit.
Claim 8
Independent Claim
184 words
An apparatus for parallel processing of image data from a local image data source, said image data including m x n image data where m and n represent the numbers of rows and columns covering a two-dimensional area of predetermined sides, the apparatus comprising: means for receiving image data sequentially; n processor stages (22) juxtaposed each including a data memory having m weight data stored therein and serving to store image data sequentially supplied via said receiving means and each including a multiplier coupled to said data memory for producing products of said image data and said weight data, said data memories in said processor stage further having m memory areas respectively and being coupled to one another in tandem so that said sequentially supplied image data are shifted sequentially between the data memories of adjacent ones of said processor stages for each individual row and that each of said data memory areas has always one image data stored therein thereby simultaneously effecting said production of products in said multipliers; and means (23) for summing the outputs of said multipliers in said processor stages.
Claim 9
Independent Claim
184 words
An apparatus for parallel processing of image data from a local image data source, said image data including m x n image data where m and n represent the numbers of rows and columns covering a two-dimensional area of predetermined sides, the apparatus comprising: means for receiving image data sequentially; n processor stages (22) juxtaposed each including a data memory having m weight data stored therein and serving to store image data sequentially supplied via said receiving means and each including a multiplier coupled to said data memory for producing products of said image data and said weight data, said data memories in said processor stage further having m memory areas respectively and being coupled to one another in tandem so that said sequentially supplied image data are shifted sequentially between the data memories of adjacent ones of said processor stages for each individual row and that each of said data memory areas has always one image data stored therein thereby simultaneously effecting said production of products in said multipliers; and means (23) for summing the outputs of said multipliers in said processor stages.
Claim 10
Independent Claim
113 words
An apparatus for parallel processing of local image data from a local image data source, comprising: means (71) for receiving local image data; memory means (79, 87) having weight data stored therein; a plurality of juxtaposed processor stages (76, 83, 88) each including a multiplier, the multipliers in said processor stages being so arranged as to be able to be simultaneously supplied with local image data via said receiving means and being coupled to said memory means for simultaneously producing products of said supplied local image data and said weight data from said memory means; and means (77, 78, 84 to 86, 89, 91, 92) for summing the outputs of said processor stages.
Claim 11
Independent Claim
113 words
An apparatus for parallel processing of local image data from a local image data source, comprising: means (71) for receiving local image data; memory means (79, 87) having weight data stored therein; a plurality of juxtaposed processor stages (76, 83, 88) each including a multiplier, the multipliers in said processor stages being so arranged as to be able to be simultaneously supplied with local image data via said receiving means and being coupled to said memory means for simultaneously producing products of said supplied local image data and said weight data from said memory means; and means (77, 78, 84 to 86, 89, 91, 92) for summing the outputs of said processor stages.
Claim 12
Independent Claim
190 words
An apparatus for parallel processing of image data from a local image data source, said image data including m x n image data where m and n represent the numbers of rows and columns covering a two-dimensional area of predetermined sides, the apparatus comprising m image data processing modules in cascade connection each responsible for image data in different one of said m rows, each of said m image data processing modules including: means (71) for receiving image data sequentially; memory means (79, 87) having n weight data stored therein; n processor stages (76, 83, 88) juxtaposed each having a multiplier coupled to said memory means, said multipliers in said juxtaposed processor stages being so arranged as to be simultaneously supplied with image data via said receiving means to simultaneously produce products of said supplied image data and the weight data from said memory means; means (77, 84, 85, 89, 91) for summing the outputs of said multipliers in said processor stages; and means (78, 86, 92) for cumulatively adding the output of said summing means and the output of the summing means of the preceding image data processing module.
Claim 13
Independent Claim
190 words
An apparatus for parallel processing of image data from a local image data source, said image data including m x n image data where m and n represent the numbers of rows and columns covering a two-dimensional area of predetermined sides, the apparatus comprising m image data processing modules in cascade connection each responsible for image data in different one of said m rows, each of said m image data processing modules including: means (71) for receiving image data sequentially; memory means (79, 87) having n weight data stored therein; n processor stages (76, 83, 88) juxtaposed each having a multiplier coupled to said memory means, said multipliers in said juxtaposed processor stages being so arranged as to be simultaneously supplied with image data via said receiving means to simultaneously produce products of said supplied image data and the weight data from said memory means; means (77, 84, 85, 89, 91) for summing the outputs of said multipliers in said processor stages; and means (78, 86, 92) for cumulatively adding the output of said summing means and the output of the summing means of the preceding image data processing module.
Claim 14
Dependent Claim
98 words
An apparatus according to Claim 8 in which each of said image data processing modules further includes n shift registers (75) provided one for each of said processor stages, the shift register for the first processor stage being coupled to said receiving means (71) for sequentially introducing said local image data from said local image data source into the apparatus, each of the other shift registers (76, 88) interconnecting two adjacent ones of said processor stages so that said sequentially introduced local image data are simultaneously supplied from said shift registers to said multipliers in said processor stages.
Claim 15
Dependent Claim
42 words
An apparatus according to Claim 9, in which said memory means in each of said image data processing modules has such a structure that different one of said n weight data is supplied to each of said multipliers in said processor stages.
Claim 16
Dependent Claim
45 words
ll. An apparatus according to Claim 9, in which said memory means in each of said image data processing modules has such a structure that said n weight data are supplied in common to each of said multipliers in said processor stages one by one.
Claim 17
Dependent Claim
42 words
An apparatus according to Claim 8, in which said receiving means (71) in each of said image data processing modules is coupled in common to each of said processor stages (83) so that image data are sequentially supplied to them in common.
Claim 18
Dependent Claim
89 words
An apparatus according to Claim 10, 11 or 12, in which in each of said image data processing modules; a pair of first pipeline registers (80) are provided for each of said processor stages (76) so that each processor stage receives input image data and delivers processed image data via one of and the other of said pair of first pipeline registers, respectiv- ly, and a second pipeline register (81) provided for said summing means (77) so that said summing means delivers its output via said second pipeline register.
Claim 19
Dependent Claim
112 words
An apparatus according to Claim 13, in which a third pipeline register (82) is provided for said adding means (78) in each of said image data processing modules so that said adding means receives the output of the adding means of the immediately preceding image data processing module via said third pipeline register, and each of the image data processing modules (70B to 70D) except the most preceding image data processing module (70A) is provided with a delay register (93) for delaying supply of the output of the summing means (77) for ensuring cumulative addition of the outputs of the adding means of said m image data processing modules in cascade connection.
References Cited (Backward Citations)
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