Patent EP0068074A2 successfully refreshed from Google Patents.
EP0068074A2
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Extremely small area PNP lateral transistor and method
Assignee: Boeing North American Inc
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Filing: 1982-03-09
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Granted: —
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Expires: 2002-03-09
Abstract
Abstract An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the action region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P<sup>+</sup> regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P<sup>+</sup> areas for the emitter and collector and oxidation fills the moat insulating regions around the active area.The oxide is stripped and the N region enhanced to N at the surface, with silox being deposited and opened for metal contacts to the N<sup>+</sup> region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.
Inventors
- 👤 Sidney Isaac Soclof
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 07:59
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
138 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: implanting N type impurities into the substrate for a given depth; masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary region beyond said depth; doping the substrate via the slotted boundary regions to a depth less than said depth to render regions of the substrate adjacent the boundary regions above said depth P+ doped; filling the doped slotted boundary regions with field oxide; doping the active region of each transistor N+ type except for the P+ portions thereof; metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 2
Independent Claim
138 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: implanting N type impurities into the substrate for a given depth; masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary region beyond said depth; doping the substrate via the slotted boundary regions to a depth less than said depth to render regions of the substrate adjacent the boundary regions above said depth P+ doped; filling the doped slotted boundary regions with field oxide; doping the active region of each transistor N+ type except for the P+ portions thereof; metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 3
Dependent Claim
25 words
The method of Claim 1, wherein: said slotting is achieved by one of ion milling and ODE etching for a (110) surface of said substrate.
Claim 4
Dependent Claim
14 words
The method of Claim 1, wherein: said implanting is a double energy arsenic implant.
Claim 5
Dependent Claim
45 words
The method of Claim 1, wherein: doping via the slotted boundary regions is achieved by ion implant at angles to the direction of the slot sufficiently less than the slot direction such that the implanting is confined to an upper portion of the slot depth.
Claim 6
Dependent Claim
18 words
The method of Claim 1, wherein: said last mentioned doping is driven into the active region by heat.
Claim 7
Dependent Claim
39 words
The method of Claim 1, wherein: said metallization and patterning is achieved by depositing a layer of silicon oxide over the substrate, and opening contact areas to each of said P+ regions and to said N+ region for metallization.
Claim 8
Dependent Claim
51 words
The method of Claim 3, wherein: the doping profile of said N and N+ regions provides a potential barrier to minimize electron flow toward the substrate surface by channelling electrons through the less heavily doped N region from one P+ region to the other P+ region in said active transistor region.
Claim 9
Dependent Claim
119 words
An array of sub-micron dimensioned PNP lateral transistors formed on a substrate doped P type, each comprising, in combination: spaced apart slots in the substrate through which P+ type doping is received into the adjacent substrate regions limited to a depth less than the slot depth; said slots filled with field oxide and surrounding each region where a transistor will be formed; said P+ doping on the inner sides of spaced apart slots within said regions comprising emitter and collector electrode areas; N doping double energy implanted in the substrate in said region separately of the P+ regions and enhanced to N+ areas to . comprise base electrode areas; and, metallization connections to each P+ and N+ electrode area.
Claim 10
Dependent Claim
119 words
An array of sub-micron dimensioned PNP lateral transistors formed on a substrate doped P type, each comprising, in combination: spaced apart slots in the substrate through which P+ type doping is received into the adjacent substrate regions limited to a depth less than the slot depth; said slots filled with field oxide and surrounding each region where a transistor will be formed; said P+ doping on the inner sides of spaced apart slots within said regions comprising emitter and collector electrode areas; N doping double energy implanted in the substrate in said region separately of the P+ regions and enhanced to N+ areas to . comprise base electrode areas; and, metallization connections to each P+ and N+ electrode area.
Claim 11
Independent Claim
95 words
The method of making a PNP lateral transistor on a p doped substrate, comprising the steps of: implanting the substrate N type using double energy implants to a certain depth, forming a recess in the substrate bounding the region for the transistor; P+ doping spaced apart portions of said region above said certain depth; N+ doping the non P+ doped portions of said region; filling said recess with field oxide; and establishing electrical connections to each of said p + spaced apart portions and to the N+ doped non P+ doped portions of said region.
Claim 12
Independent Claim
95 words
The method of making a PNP lateral transistor on a p doped substrate, comprising the steps of: implanting the substrate N type using double energy implants to a certain depth, forming a recess in the substrate bounding the region for the transistor; P+ doping spaced apart portions of said region above said certain depth; N+ doping the non P+ doped portions of said region; filling said recess with field oxide; and establishing electrical connections to each of said p + spaced apart portions and to the N+ doped non P+ doped portions of said region.
Claim 13
Dependent Claim
85 words
A PNP transistor having an active region formed on a P substrate, comprising the steps of: implanting the substrate N type using double energy implants to a certain depth; recessing the substrate substantially along the periphery of the transistor active region; selectively doping the transistor active region through portions of the recesses formed by said recessing; filling said recesses with substrate oxide to isolate the active region from said substrate; and, forming conductors to different portions of said active region to serve as electrode connections.
Claim 14
Dependent Claim
85 words
A PNP transistor having an active region formed on a P substrate, comprising the steps of: implanting the substrate N type using double energy implants to a certain depth; recessing the substrate substantially along the periphery of the transistor active region; selectively doping the transistor active region through portions of the recesses formed by said recessing; filling said recesses with substrate oxide to isolate the active region from said substrate; and, forming conductors to different portions of said active region to serve as electrode connections.
Claim 15
Dependent Claim
24 words
The transistor of Claim 10, wherein: said selectively doping comprises introducing P+ type doping into the substrate via the upper sidewalls of the recesses.
Claim 16
Dependent Claim
25 words
The transistor of Claim 11, wherein: said doping is achieved by angle implanting the substrate via said recesses to a predetermined depth along the recesses.
Claim 17
Dependent Claim
29 words
The transistor of Claim 12, further comprising: N doping diffused into the active region between the P+ doped regions adjacent the substrate surface enhanced to N+ for current control.
References Cited (Backward Citations)
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