Patent EP0068072A2 successfully refreshed from Google Patents.
EP0068072A2
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EP
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Lateral PNP transistor and method
Assignee: Boeing North American Inc
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Filing: 1982-03-09
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Granted: —
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Expires: 2002-03-09
Abstract
Abstract The invention is a sub-micron dielectrically isolated PNP transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single P doped chip with each transistor comprising an active region surrounded by field oxide regions, P + spaced-apart doped portions within said active regions and oxide plus N doping surrounding each P + region; electrical connections to the base N portion and the collector and emitter P + portions. These regions are established by first forming boundary recesses about each active portion where a transistor will be formed, depositing boron in the recesses to form P + regions in the transistor-active region adjacent the recesses, deepening the recesses, diffusing aresenic into the deepened recesses to dope the substrate N type beneath the P + regions and also between the P + regions, and patterning and metallizing the substrate to develop the electrical connections of the base, emitter and collector electrodes. Optionally, the substrate may be N + doped adjacent its surface, between the collector and emitter, to force current flow away from the surface.
Inventors
- 👤 Sidney Isaac Soclof
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:27
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D10/00; H10D10/60; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
142 words
An array of sub-micron dimensioned PNP lateral transistors formed on a substrate P doped, each comprising in combination: spaced apart slots in the substrate through which N type doping is received into the adjacent substrate to N dope the transistor active region of the substrate; said slots filled with field oxide and surrounding each region where a transistor will be formed; and, P+ doping on the inner sides of the spaced apart slots within said regions comprising emitter and collector electrode areas; said slots deepened into the original p substrate; said slots filled with field oxide and surrounding each region where a transistor will be formed; and, N doping implanted in the substrate in said active region separately of the P+ regions and enhanced to N+ areas to comprise base electrode areas; and, metallization connections to each P+ and N+ electrode area.
Claim 2
Dependent Claim
142 words
An array of sub-micron dimensioned PNP lateral transistors formed on a substrate P doped, each comprising in combination: spaced apart slots in the substrate through which N type doping is received into the adjacent substrate to N dope the transistor active region of the substrate; said slots filled with field oxide and surrounding each region where a transistor will be formed; and, P+ doping on the inner sides of the spaced apart slots within said regions comprising emitter and collector electrode areas; said slots deepened into the original p substrate; said slots filled with field oxide and surrounding each region where a transistor will be formed; and, N doping implanted in the substrate in said active region separately of the P+ regions and enhanced to N+ areas to comprise base electrode areas; and, metallization connections to each P+ and N+ electrode area.
Claim 3
Dependent Claim
28 words
The transistor of Claim 1, wherein: said region is substantially rectangular having a length of 5d and a width of 4d wherein d is 0.4 to 1 micrometer.
Claim 4
Dependent Claim
68 words
The transistor of Claim 1, wherein; the P+ doping is diffused through said slots after they have been deepened following the N doping in order that the P doping underlies the P+ doping and the N doping is between the P+ doping; and, the N doping is diffused through the substrate surface in said regions at least between P± doped substrate area to comprise the enhanced N+ regions.
Claim 5
Dependent Claim
28 words
The transistor of Claim 2, wherein; N+ doping is implanted through said substrate surface in said regions at least between P+ doped substrate areas after said P+ diffusion.
Claim 6
Dependent Claim
32 words
The transistor of Claim 1, wherein; the P+ doping is diffused through said slots after the N doping overlies the substrate P doping; and, slots are deepened into said original P substrate,
Claim 7
Dependent Claim
25 words
The transistor of Claim 5, wherein; N doping is implanted through said substrate surface in said region over the N doping to comprise N+ regions,
Claim 8
Independent Claim
142 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary regions; doping the substrate via the slotted boundary regions to render regions of the substrate adjacent the boundary regions N doped; doping the substrate via the slotted boundary regions to render regions of the substrate adjacent thereto P+ regions; deepening the slotted boundary regions into the original P doped substrate; filling the deepened slotted boundary regions with field oxide; optionally doping the regions adjacent the substrate surface between the P+ regions N+; and, metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 9
Independent Claim
142 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary regions; doping the substrate via the slotted boundary regions to render regions of the substrate adjacent the boundary regions N doped; doping the substrate via the slotted boundary regions to render regions of the substrate adjacent thereto P+ regions; deepening the slotted boundary regions into the original P doped substrate; filling the deepened slotted boundary regions with field oxide; optionally doping the regions adjacent the substrate surface between the P+ regions N+; and, metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 10
Dependent Claim
15 words
The method of Claim 7, wherein; said slotting and deepening is effected by ion milling.
Claim 11
Dependent Claim
28 words
The method of Claim 8, wherein; said P+ doping is achieved by diffusion following oxidation of the substrate and removal of the oxide from the slotted boundary regions.
Claim 12
Dependent Claim
16 words
The method of Claim 9, wherein; said N doping is achieved by implanting arsenic or phosphorous
Claim 13
Independent Claim
79 words
The method of making a PNP lateral transistor on a P doped substrate, comprising the steps of: forming a recess in the substrate bounding the region for the transistor; N doping the substrate adjacent said region; P+ doping spaced apart portions of said regions; Deepening the recess into the original P substrate; filling said recess with field oxide; and, establishing electrical connections to each of said P+ spaced apart portions and to the N doped portion of said region.
Claim 14
Independent Claim
79 words
The method of making a PNP lateral transistor on a P doped substrate, comprising the steps of: forming a recess in the substrate bounding the region for the transistor; N doping the substrate adjacent said region; P+ doping spaced apart portions of said regions; Deepening the recess into the original P substrate; filling said recess with field oxide; and, establishing electrical connections to each of said P+ spaced apart portions and to the N doped portion of said region.
Claim 15
Dependent Claim
101 words
A PNP transistor having an active region formed on a P doped substrate, comprising the steps of; recessing the substrate substantially along the periphery of the transistor active region; N doping the transistor active region via portions of said recessing; selectively P doping the transistor active region through portions of the recesses formed by said recessing to form P+ regions; deepening the recessing into said P substrate; filling said recesses with substrate oxide substantially to isolate the active region from said substrate; and, forming conductors to different portions of said active region to serve as emitter, base and collector electrode connections.
Claim 16
Dependent Claim
101 words
A PNP transistor having an active region formed on a P doped substrate, comprising the steps of; recessing the substrate substantially along the periphery of the transistor active region; N doping the transistor active region via portions of said recessing; selectively P doping the transistor active region through portions of the recesses formed by said recessing to form P+ regions; deepening the recessing into said P substrate; filling said recesses with substrate oxide substantially to isolate the active region from said substrate; and, forming conductors to different portions of said active region to serve as emitter, base and collector electrode connections.
Claim 17
Dependent Claim
24 words
The transistor of Claim 12, wherein: The emitter and collector regions are the P doped regions; and, the base region is enhanced to N+.
References Cited (Backward Citations)
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