Abstract A current mirror circuit in which error between input current (lin) and output current (lout) is small and which can operate with low voltage. First and second current mirror transistors (Q1, Q2) of a first conductivity type have their emitters each connected to a power supply, their bases connected together and their collectors connected to an input terminal (11) and an output terminal (12) respectively. A current amplification factor compensating third transistor (Q4) of the first conductivity type is provided which has its emitter connected to the bases of the first and second transistors and its collector connected to a reference potential point. A fourth transistor (Q3) of a second conductivity type is provided for level shifting. This transistor (Q3) has its collector connected to the emitters of the first and second transistors, its emitter connected to the base of the third transistor and its base connected to the collector of the first transistor. A current source (IS) is connected between the third transistor and the reference potential point.
A current mirror circuit in which first and second transistors (Ql, Q2) of a first conductivity type are provided which have their emitters connected to a power supply (Vcc), their bases connected together and their collectors respectively connected to a current input terminal (11) and a current output terminal (12) and a third transistor (Q4) of the first conductivity type is provided which has its emitter connected to the bases of said first and second transistors (Ql, Q2), its collector connected to a reference potential point, characterized in that a fourth transistor (Q3) of a second conductivity type complementary to the first conductivity type is provided which has its collector connected to the emitters of said first and second transistors (Ql, Q2), its emitter connected to the base of said third transistor (Q4) and its base connected to the collector of said first transistor (Ql), and a current source (IS) is connected between the base of said third transistor and the reference potential point.
Claim 2
Dependent Claim
164 words
A current mirror circuit in which first and second transistors (Ql, Q2) of a first conductivity type are provided which have their emitters connected to a power supply (Vcc), their bases connected together and their collectors respectively connected to a current input terminal (11) and a current output terminal (12) and a third transistor (Q4) of the first conductivity type is provided which has its emitter connected to the bases of said first and second transistors (Ql, Q2), its collector connected to a reference potential point, characterized in that a fourth transistor (Q3) of a second conductivity type complementary to the first conductivity type is provided which has its collector connected to the emitters of said first and second transistors (Ql, Q2), its emitter connected to the base of said third transistor (Q4) and its base connected to the collector of said first transistor (Ql), and a current source (IS) is connected between the base of said third transistor and the reference potential point.
Claim 3
Dependent Claim
30 words
The current mirror circuit according to claim 1 wherein a resistor (R) is connected between the emitter of said fourth transistor (Q3) and the base of said third transistor (Q4).
Claim 4
Dependent Claim
53 words
The current mirror circuit according to claim 2 wherein a fifth transistor (Q5) of the first conductivity type is provided which has its emitter connected to the collector of said second transistor (Q2), its collector connected to said output terminal (12) and its base connected to the emitter of said fourth transistor (Q3).
Claim 5
Dependent Claim
27 words
The current mirror circuit according to claim 1, 2 or 3 wherein the first conductivity type is PNP type and the second conductivity type is NPN type.
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