Self-calibration of analog-to-digital converters

Claim 2

In a data acquisition system, comprising a weighted array of components having a common node circuit means connected to said node for determining the mismatch between said components and producing an error correcting signal to said node to substantially correct the effects of said mismatch.

Claim 3

The system of Claim 1 wherein said components are binary weighted.

Claim 4

The system of Claim 1 wherein said components are capacitors.

Claim 5

The system of Claim 1 wherein said components are resistors.

Claim 6

A self calibrating charge-redistribution analog-to-digital converter comprising a first binary weighted capacitor array having a plurality of capacitors, one plate of each of said capacitors being electrically connected to a node, a comparator. having one input electrically connected to said node, first logic means connected to said comparator output and said array for selectively connecting said capacitors to preselected voltages, and at least a second binary weighted er-ror capacitor array electrically connected to said node and having a plurality of capacitors for determining the error correcting signal required at said node to correct the binary mismatch of preselected capacitors in said first array.

Claim 7

A self calibrating charge-redistribution analog-to-digital converter comprising a first binary weighted capacitor array having a plurality of capacitors, one plate of each of said capacitors being electrically connected to a node, a comparator. having one input electrically connected to said node, first logic means connected to said comparator output and said array for selectively connecting said capacitors to preselected voltages, and at least a second binary weighted er-ror capacitor array electrically connected to said node and having a plurality of capacitors for determining the error correcting signal required at said node to correct the binary mismatch of preselected capacitors in said first array.

Claim 8

A converter according to Claim 5 further including second logic means connected to said error capacitor array for reproducing a digital representation of said error signal which causes said second error capacitor array to produce the analog representation of said error signal at said node each time said preselected mismatched capacitors are utilized in said first array.

Claim 9

A converter according to Claim 5 wherein one plate of each said capacitors in said error capacitor array is connected through a scaling capacitor to said node.

Claim 10

A converter according to Claim 5 wherein said first binary array includes one additional capacitor which is equal to LSB capacitor.

Claim 11

A converter according to Claim 5 further including a predetermined number of additional binary weighted error capacitor array electrically connected to said node, each having a plurality of capacitors, each of said arrays determining the error signal required at said node to correct the binary mismatch of preselected capacitors of said array.

Claim 12

A converter according to Claim 9 wherein said predetermined number of error capacitor arrays corrects the capacitor in said first array associated with the MSB and a selected number of the more significant bits.

Claim 13

ll. A converter according to Claim 9 further including logic means connected .to each of said predetermined number of error capacitor arrays for producing a digital signal to each of said error capacitor arrays representative of the mismatch of said preselected capacitors.

Claim 14

A converter according to Claim 11 wherein each of said digital signals from said respective logic means is input to its respective error capacitor array to produce an analog error signal representative of the mismatch of the binary weighted capacitors in said first array.

Claim 15

A converter according to Claim 5 further including a memory means interconnected between said first and second logic means for storing the digital representations of the mismatch in the binary weighted capacitors in said first array.

Claim 16

A converter according to Claim 13 wherein said memory has storage capacity of 2 N where N equals the number of bits to be corrected.

Claim 17

A converter according to Claim 13 wherein said memory has storage capacity of N, where N equals the number of bits to be corrected.

Claim 20

. 17. A method of calibrating a binary weighted component array having a common node to which is connected an error correcting circuit, comprising the steps of: 1) applying a signal of one polarity and magnitude to a first component in the array and applying a second signal of opposite polarity but same magnitude to the second component in the array with the resulting signal E at the common node proportional to the error in said second component, 2) converting signal E 1 into a digital signal for storing, 3) applying a third signal of one polarity and magnitude to the first and second component of the array and a . fourth signal of opposite polarity but same polarity to the third component of said array, 4) converting E 1 into an analog form and.apply said analog signal to said common node with the resulting analog signal E 2 at the common node being proportional to the binary mismatch between said third component and said first and second components, and 5) converting E 2 into a digital signal for storage.

Claim 21

. 17. A method of calibrating a binary weighted component array having a common node to which is connected an error correcting circuit, comprising the steps of: 1) applying a signal of one polarity and magnitude to a first component in the array and applying a second signal of opposite polarity but same magnitude to the second component in the array with the resulting signal E at the common node proportional to the error in said second component, 2) converting signal E 1 into a digital signal for storing, 3) applying a third signal of one polarity and magnitude to the first and second component of the array and a . fourth signal of opposite polarity but same polarity to the third component of said array, 4) converting E 1 into an analog form and.apply said analog signal to said common node with the resulting analog signal E 2 at the common node being proportional to the binary mismatch between said third component and said first and second components, and 5) converting E 2 into a digital signal for storage.

Claim 22

A method of calibrating capacitors C 1 -C N in an A/D-D/A having a binary weighted capacitor array C 1 (LSB), C 2 , C 3 , C 4 ...C N (MSB) plus one additional capacitor C o of weight corresponding to the least significant bit (LSB) in combination with an error correcting capacitor array combined at an analog summation node, comprising the steps of: 1) initializing the summation node to zero, 2) applying a first signal of one polarity and magnitude to C 0 and a second signal of opposite polarity but same magnitude to C 1 with the resulting signal E 1 at the summing node being proportional to the error in capacitor C l , 3) converting signal E 1 into a digital signal using said error correcting capacitor array, 4) initializing the summation node again to zero, 5) applying a third signal of one polarity and magnitude to Co and C 1 and a fourth signal of opposite polarity but same magnitude to C 2 , 6) converting'E l into an analog signal using said error correcting capacitor array and applying said analog signal E 1 to said summing node, with the resulting analog signal E 2 at the summing node being proportional to the error. in C 2 , 7) converting E 2 into a digital signal using said error correcting capacitor array, and Claim 18, continued 8) repeating steps 4) - 7) for the remaining capacitors as required.