Output circuit

Claim 1

An output circuit comprising a first terminal (4) for connection to a first potential, a second terminal for connection to a second potential, an output terminal (5), a first insulated gate field effect transistor (Q 1 ) connected between said first terminal and said output terminal and having a gate supplied with a first signal, a second insulated gate field effect transistor (Q 2 ) connected between said second terminal and said output terminal (5) and having a gate supplied with a second signal having an opposite phase to said first signal, and means (Q 3 , Q 4 ) responsive to a control signal for forcibly clamping the potentials at the gates of said first and second field effect transistors (Q 1 , Q 2 ) to said second potential, characterised in that a third field effect transistor (Q 5 ) is inserted between said first insulated gate field effect transistor (Q 1 ) and said first terminal, (4), said third field effect transistor (Q 5 ) having a gate supplied with a potential that causes said third field effect transistor (Q 5 ) to have a high internal resistance at least when said clamping means clamps the potentials at the gates of said first and second field effect transistors (Q 1 , Q 2 ) to said second potential.