Multicomputer system and transmission control method therefor

Claim 2

A multicomputer system comprising: (a) first and second computers (1,2), each of which includes a processor (1002) for controlling transmission and reception of data, and a memory (1003) for storing data received and to be transmitted; (b) a bidirectional common transmission bus (100); (c) first and second bus (10, 20) connector means, which are respectively connected to said common transmission bus (100) and each of which includes gate means .(103...108) for selectively passing a signal to enter the corresponding computer from said common transmission bus (100) and a signal to be delivered from said corresponding computer to said common transmission bus; (d) a first control line (1020) and a first data bus (1010) which connect said first computer (1) with said first bus connector means (10); (e) a second control line (2020) and a second data bus (2010) which connect said second computer (2) with said second bus connector means (20), said gate means (103... 108) being controlled by control signals which are applied from the respective computers to said bus connector means through the respective control lines, and data delivered from said first computer (1) being transmitted to said second computer through said first data bus (1010), said first bus connector means (10), said common transmission bus (100), said second bus connector means (20) and said second data bus (2010); (f) a third control line (120) which connects said first with second computers (1, 2); and (g) a closed loop for transmitting a signal for checking any fault of the computer and which includes said first computer (1), said third control line (120), said second computer (2), said second data bus (2010), said second bus connector means (20), said common transmission bus (100), said first bus connector means (10) and said first data bus (1010).

Claim 3

A multicomputer system according to claim 1, wherein said memory (1003) of said each computer .(1, 2) has an area for storing a status flag. (10031), and said gate means (103...108) of said each bus connector means (10,20) is controlled by a control signal corresponding to said status flag.

Claim 4

A multicomputer system according to claim 1 or 2, wherein said memory (1003) of said each computer (1, 2) has an area (10035) for storing a value corresponding to a predetermined time, said each computer (1, 2) further includes first timer means (10041) for counting a period of time from the reception of a transmission request signal, and the fault of the computer (1, 2) is sensed on the basis of a result of comparison between an output of said first timer means (10041) and the aforementioned predetermined value.

Claim 5

A multicomputer system according to any of claims 1 to 3, wherein said memory (1003) of said each computer (1, 2) has an area (10036) for storing a value corresponding to a predetermined time, said each computer (1, 2) further includes first timer means (10042) for counting a time interval from the time that predetermined data are delivered onto said data bus (1010, 2010) to the time that the data return back to the same computer (1, 2), and said gate means (103...108) of said each bus connector (10, 20) is controlled so that, when an output of said timer means.(10042) has become greater than the aforementioned predetermined-value, no data may be delivered from the particular computer (1, 2). to said common data transmission bus (100).

Claim 6

A multicomputer system according to any of claims 1 to 4, wherein said memory (1003) of said each computer (1, 2) has an area (10036) for storing a value corresponding to a predetermined time, said each computer (1, 2) further includes second timer means (1.0042) for counting a time interval from the time that the signal is delivered to said third control line (120) of said closed loop to the time that the signal returns back to the same computer (1, 2), and said gate means (103...108) of said each bus connector (10, 20) is controlled so that, when an output of said timer means (10042) has become greater than the aformentioned predetermined value, no data may enter the particular computer (1, 2) from at least one direction of said common data transmission bus (100).

Claim 7

A multicomputer system comprising: (a) first and second bidirectional data transmission buses (100, 200); (b) a plurality of computers (1...4), each of which includes first and second processors (1101, 2101) for controlling transmission and reception of data, and a memory (1003) for storing data received and to be transmitted; (c) a group of first bus connector means (11...14) which are connected to said first data transmission bus (100), and each of which includes first gate means (113...118) for controlling passage of data to enter said first processor (1101) of one of said computers (1...4) from said first data transmission bus (100) and data to be delivered from said first processor to said first data transmission bus; (d) a group of second bus connector means (.21...24) which are connected to said second data transmission bus (200), and each of which includes second gate means (213...218) for controlling passage of data to enter said second processor (2101) of one of said computers (1...4) from said second data transmission bus (200) and data to be delivered from said second processor to said second data transmission bus; (e) a first control line (11020) and a first data bus (11010) which connect said first bus connector means (11...14) with said first processor .(1101) of one of said computers (1...4); (f) a second control line (21020) and a second data bus (21010) which connect said second bus connector means (21...24) with said second processor (2101) of one of said computers (1...4); (g) a third control line (1n10...1450) which connects said first processor (1101) of one of said computers (1...4) with said first processor of another computer; (h) a fourth control line (2n20...2450) which connects said second processor (2101) of one of said computers (1...4) with said second processor of another computer; and (i) first and second closed loops for checking any fault of the computer, said each first closed loop including the first processors (1101) of two of said computers (1, 2) and the first bus connector means (11 , 12) and third control lines (1120)connected to the respective processors, said each second closed loop including the second processors (2101) of two of said computers (1, 2) and the second bus connector means..(21, 22) and fourth control lines (2120) connected to the respective processors.

Claim 8

A multicomputer system comprising: (a) first and second bidirectional data transmission buses (100, 200); (b) a plurality of computers (1...4), each of which includes first and second processors (1101, 2101) for controlling transmission and reception of data, and a memory (1003) for storing data received and to be transmitted; (c) a group of first bus connector means (11...14) which are connected to said first data transmission bus (100), and each of which includes first gate means (113...118) for controlling passage of data to enter said first processor (1101) of one of said computers (1...4) from said first data transmission bus (100) and data to be delivered from said first processor to said first data transmission bus; (d) a group of second bus connector means (.21...24) which are connected to said second data transmission bus (200), and each of which includes second gate means (213...218) for controlling passage of data to enter said second processor (2101) of one of said computers (1...4) from said second data transmission bus (200) and data to be delivered from said second processor to said second data transmission bus; (e) a first control line (11020) and a first data bus (11010) which connect said first bus connector means (11...14) with said first processor .(1101) of one of said computers (1...4); (f) a second control line (21020) and a second data bus (21010) which connect said second bus connector means (21...24) with said second processor (2101) of one of said computers (1...4); (g) a third control line (1n10...1450) which connects said first processor (1101) of one of said computers (1...4) with said first processor of another computer; (h) a fourth control line (2n20...2450) which connects said second processor (2101) of one of said computers (1...4) with said second processor of another computer; and (i) first and second closed loops for checking any fault of the computer, said each first closed loop including the first processors (1101) of two of said computers (1, 2) and the first bus connector means (11 , 12) and third control lines (1120)connected to the respective processors, said each second closed loop including the second processors (2101) of two of said computers (1, 2) and the second bus connector means..(21, 22) and fourth control lines (2120) connected to the respective processors.

Claim 9

A multicomputer system according to claim 6, wherein said memory (1003) of said each computer (1...4) has an area (100321) for storing a transfer direction flag, and said first gate means (113...118) or second gate means (213...218) is controlled so as to deliver data from the computer '(1...4) to said first data transmission bus (100) or second data transmission bus (200) in correspondence with said flag.

Claim 10

A multicomputer system according to claim 6 or 7, wherein said memory of said each computer (1...4) has a data buffer area (1005), and data received through said first data bus (11010) are stored in said area and are thereafter delivered.from the computer (1...4) through said second data bus (21010).

Claim 11

In a multicomputer system including a plurality of computers (1...3) each of which has a processor (1001) for controlling transmission and reception of data and a memory (1003) which stores data received and to be transmitted, a bidirectional common transmission bus (100), gate means (103...108) which is connected between said each computer (1...3) and said common transmission bus (100), and a control line (120, 230, 340) which connects the respective adjacent computers; a transmission control method comprising: the step of counting a time interval in which predetermined data delivered from any desired one of said computers (1...3) reach another computer, the step of controlling said gate means (103...108) when said time interval is greater than a predetermined time, so that no data may be delivered from said one computer to said common transmission bus (100), the step of delivering a fault check signal from one of said computers (1...3) to the adjacent computer through said control line (120, 230, 340), the step of counting a time interval in which the delivered fault check signal returns to the original computer (1...3) through the adjacent computer, said common transmission bus (100) and aid gate means (103... 108), and the step of controlling said gate means (103...108) connected between said common transmission bus (100) and said computer (1...3) having delivered said fault check signal, so as to.be in Cut off state when said time interval is greater than a predetermined time.

Claim 12

In a multicomputer system including a plurality of computers (1...3) each of which has a processor (1001) for controlling transmission and reception of data and a memory (1003) which stores data received and to be transmitted, a bidirectional common transmission bus (100), gate means (103...108) which is connected between said each computer (1...3) and said common transmission bus (100), and a control line (120, 230, 340) which connects the respective adjacent computers; a transmission control method comprising: the step of counting a time interval in which predetermined data delivered from any desired one of said computers (1...3) reach another computer, the step of controlling said gate means (103...108) when said time interval is greater than a predetermined time, so that no data may be delivered from said one computer to said common transmission bus (100), the step of delivering a fault check signal from one of said computers (1...3) to the adjacent computer through said control line (120, 230, 340), the step of counting a time interval in which the delivered fault check signal returns to the original computer (1...3) through the adjacent computer, said common transmission bus (100) and aid gate means (103... 108), and the step of controlling said gate means (103...108) connected between said common transmission bus (100) and said computer (1...3) having delivered said fault check signal, so as to.be in Cut off state when said time interval is greater than a predetermined time.