Patent EP0062170A2 successfully refreshed from Google Patents.
EP0062170A2
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EP
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Process for forming self-aligned dielectric isolation
Assignee: International Business Machines Corp
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Filing: 1982-03-09
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Granted: —
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Expires: 2002-03-09
Abstract
Abstract There is provided a process for manufacturing high density integrated circuits where transistor emitter-base isolation distances are established with high precision and, if there is any misalignment during photolithographic procedures, such misalignment occurs in a wide dielectric isolation without adverse impact on transistor performance. The process comprises: a) producing an ion-implantation resistant island on a substrate; b) growing ion-implantation resistant sidewalls on the island; c) implanting a first impurity; d) removing the sidewalls; e) implanting a second impurity where the sidewalls were; f) growing a conformal etchable coating over the surface of the device; g) masking to define an area spaced from and exterior to the area where the sidewalls were; h) removing the conformal etchable coating in the area of step g); i) etching a deep trench in the area where the conformal coating was removed; j) implanting a third impurity into the deep trench; k) filling said deep trench (47a, b) with a dielectric material. Following island removal, the emitter and base of a bipolar transistor are formed in the area where the island existed.
Inventors
- 👤 Klaus Dietrich Beyer
- 👤 Joseph Skinner Logan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 20:53
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10D; H10D10/00; H10D10/40; H10D10/441; H10P; H10P76/00; H10P76/40; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; Y; Y10; Y10S; Y10S148/00; Y10S148/131
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
327 words
A method of forming self-aligned dielectric isolation in a semiconductor silicon substrate, characterized by the following steps: (a) forming an epitaxial layer (11) on said substrate (10); (b) forming a polysilicon layer (12) over said epitaxial layer (11); (c) forming an ion implantation masking rectangular island (18) on said polysilicon layer (12); (d) forming ion implantation masking side walls (20a, b; 21a, b) on said diffusion-resistant rectangular island (18); (e) implanting a first impurity into areas (22) not covered by said island (18) or said side walls (20a, b; 21a, b); (f) forming an ion implantation masking layer (24) on said silicon substrate at areas other than at said diffusion-resistant side walls and abutting said side walls; (g) removing said side walls (20a, b; 21a, b); (h) implanting a second impurity only in the area (25a, b) where said side walls were removed, said island (18) and said masking layer (24) preventing implantation into areas other than where said side walls were removed; (i) etching a gap through said polysilicon layer (12) at the areas (25a, b) where side walls were removed;. (j) covering the surface of said device with an etchable dielectric material (30), which etchable dielectric material also covers said exposed silicon layer (11); (k) selectively masking and then removing said etchable dielectric material (30) in areas other than in said island (38), said gap, and an area contiguous to said gap, whereby said etchable dielectric material is removed in a prospective deep trench area (38a, b) surrounding but spaced from said gap by said area contiguous said gap; (1) etching a deep trench (47a, b) into said silicon substrate where said etchable dielectric material (30) was removed from said prospective deep trench area, said deep trench being spaced from said island (18) by said gap and said area contiguous to said gap; (m) implanting a third impurity (47, 46) into said deep trench; (n) filling said deep trench with a dielectric isolation material (48).
Claim 2
Independent Claim
327 words
A method of forming self-aligned dielectric isolation in a semiconductor silicon substrate, characterized by the following steps: (a) forming an epitaxial layer (11) on said substrate (10); (b) forming a polysilicon layer (12) over said epitaxial layer (11); (c) forming an ion implantation masking rectangular island (18) on said polysilicon layer (12); (d) forming ion implantation masking side walls (20a, b; 21a, b) on said diffusion-resistant rectangular island (18); (e) implanting a first impurity into areas (22) not covered by said island (18) or said side walls (20a, b; 21a, b); (f) forming an ion implantation masking layer (24) on said silicon substrate at areas other than at said diffusion-resistant side walls and abutting said side walls; (g) removing said side walls (20a, b; 21a, b); (h) implanting a second impurity only in the area (25a, b) where said side walls were removed, said island (18) and said masking layer (24) preventing implantation into areas other than where said side walls were removed; (i) etching a gap through said polysilicon layer (12) at the areas (25a, b) where side walls were removed;. (j) covering the surface of said device with an etchable dielectric material (30), which etchable dielectric material also covers said exposed silicon layer (11); (k) selectively masking and then removing said etchable dielectric material (30) in areas other than in said island (38), said gap, and an area contiguous to said gap, whereby said etchable dielectric material is removed in a prospective deep trench area (38a, b) surrounding but spaced from said gap by said area contiguous said gap; (1) etching a deep trench (47a, b) into said silicon substrate where said etchable dielectric material (30) was removed from said prospective deep trench area, said deep trench being spaced from said island (18) by said gap and said area contiguous to said gap; (m) implanting a third impurity (47, 46) into said deep trench; (n) filling said deep trench with a dielectric isolation material (48).
Claim 3
Dependent Claim
41 words
The method of Claim 1, characterized in that the masking of step (k) is a photolithographic masking which results in photoresist over at least a portion of said island (18) and over the area immediately outside said prospective deep trench area.
Claim 4
Dependent Claim
67 words
The method of Claim 1 or 2, characterized in that said island (18) comprises, in sequence from said substrate, a lower Si 3 N 4 layer (15), a doped Sio 2 layer (16) and an upper polysi layer (17), wherein during formation of said prospective deep trench area if said misalignment occurs said island unprotected by photoresist is not removed beyond said doped SiO 2 layer (15).
Claim 5
Independent Claim
73 words
The method of any one of the Claims 1 to 3, characterized in that said etchable dielectric material (30) is conformal to all surfaces on which it is formed, whereby it has a thickness over said island, said gap and said area contiguous said gap so that upon removal thereof from said prospective deep trench area said etchable dielectric material still remains over said island, said gap, and said area contiguous said gap.
Claim 6
Independent Claim
45 words
The method of any one of the Claims 1 to 4, characterized in that as said deep trench is filled with said dielectric isolation material (48) in step (n) the entire surface of the device is coated with said dielectric isolation material, which is etchable.
Claim 7
Dependent Claim
62 words
The method of Claim 5, characterized in that said dielectric isolation material (48) is further coated with a photoresist which is selectively removed in an area at substantially a 90° angle to said deep trench, whereafter a shallow trench of a lesser depth than said deep trench is etched into said epitaxial layer (11) at the area wherein said photoresist was removed.
Claim 8
Dependent Claim
47 words
The method of Claim 3, characterized in that there is formed over said polysilicon layer (12) and under said island (18), in sequence, a Si 3 N 4 layer (13) and a second polysilicon layer (14), said island (18) being formed on said second polysilicon layer (14).
Claim 9
Dependent Claim
71 words
The method of Claim 7, characterized in that said lower Si 3 N 4 layer (15) and said doped Si0 2 layer (16) of said island (18) are removed, whereafter said second polysilicon layer (14) and said Si 3 N 4 layer (13) under said island are removed to expose said polysilicon layer (12) under said island (18), whereafter transistor emitter and base implantations are conducted through said polysilicon layer (12).
Claim 10
Independent Claim
46 words
The method of any one of the Claims 1 to 8, characterized in that said side walls comprise in a third polysilicon layer (19), an Si 3 N 4 layer (20) and an area of Si0 2 (21) over said Si 3 N 4 layer (20).
References Cited (Backward Citations)
No citation records indexed.
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