Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
85 words
Store-in-cache multiprocessor (MP) system with checkpoint feature, where each processor (CP) has associated a store-in-cache (SIC) and a cache directory (PD) and where changed cache lines are locked until the next checkpoint occurs, characterized in that a lock bit (L) is provided in the cache directory entry for each cache line, that the lock bit is set under processor control and that for line replacement the lock bits are evaluated to select only unlocked lines in each set- _ associative congruence class within the cache.
Claim 2
Dependent Claim
85 words
Store-in-cache multiprocessor (MP) system with checkpoint feature, where each processor (CP) has associated a store-in-cache (SIC) and a cache directory (PD) and where changed cache lines are locked until the next checkpoint occurs, characterized in that a lock bit (L) is provided in the cache directory entry for each cache line, that the lock bit is set under processor control and that for line replacement the lock bits are evaluated to select only unlocked lines in each set- _ associative congruence class within the cache.
Claim 3
Dependent Claim
57 words
Multiprocessor system according to claim 1, characterized in that the lock bits are contained in a lock array (10) being arranged with the same number of congruence classes and set associativity (A, B, C, D) as the cache directory (PD-62) and that all lock bits in the lock array are reset in response to each checkpoint signal.
Claim 4
Dependent Claim
61 words
Multiprocessor system according to claim 1 or 2, characterized in that a least-recently-used (LRU) replacement mechanism (LRU array 42) is used within each set-associative congruence class delivering select signals (R, S, T) to a LRU lock selection control (12) which also recieves the lock bits for the same congruence class from lock array (10) to generate modified LRU selection parameters (R'S'T').
Claim 5
Dependent Claim
56 words
Multiprocessor system according to claim 3, characterized in that 4-set-associative congruence - classes (A, B, C, D) are provided and that the outputs (R, S, T) of the LRU array (42) are modified in the LRU lock selection control (12) according to the following table to generate the modified LRU selection signals (R', S', T') :
Claim 6
Dependent Claim
38 words
Multiprocessor system according to any one of the claims 1 - 4, characterized in that the lock bit (L) of a cache line is set by a processor instruction (S1) initi- ating a cache fetch or store operation.
Claim 7
Dependent Claim
33 words
Multiprocessor system according to any one of the claims 1 - 5, characterized in that the execution of a checkpoint operation is requested whenever all lines in any congruence class have become locked.
Claim 8
Dependent Claim
50 words
Multiprocessor system according to any one of the claims 1 - 6, characterized in that locked lines detected in the cache of another processor in the multiprocessor system during a cross-interrogation operation are blocked from being castout or invalidated until their lock bit is turned off at a next checkpoint.
Claim 9
Dependent Claim
36 words
Multiprocessor system according to any one of the claims 1 - 7, characterized in that the lock bit is set by the processor in storage operations requiring independence of other processors in instruction execution (ato- micity).
Claim 10
Dependent Claim
40 words
Multiprocessor system according to any one of the claims 1 - 8, characterized in that a potential deadlock signal is generated (circuits 181-183, Fig. 14) and transferred to system control circuits (SUP) whenever two processors detect concurrent conflicting locked lines.
Claim 11
Dependent Claim
37 words
Multiprocessor system according to any one of the claims 1 - 9, characterized in that the cache directory (PD) entry for each cache line contains an Ex-bit, designating the line as exclusively reserved for the associated processor.