Patent EP0060408A1 successfully refreshed from Google Patents.
EP0060408A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Electrically erasable programmable read only memory
Assignee: Toshiba Corp
•
Filing: 1982-02-19
•
Granted: —
•
Expires: 2002-02-19
Abstract
Abstract In an electrically erasable and programmable read only memory (E 2 PROM) of this invention, each memory cell (14) has an L-shaped floating gate (28) insulated from a substrate. The floating gate (28) and a first control gate (36), the floating gate (28) and a second control gate (46), and the floating gate (28) and a source electrode (32) connected to a source (26) are capacitively coupled at predetermined capacitances, respectively. A projecting portion (34) which is formed in the source electrode (32) underlies a coupling region of first and second gate portions (28-1 and 28-2) of the floating gate (28). When a voltage of +20 V if applied to the source electrode (32) and a voltage of 0 V is applied to the first and second gates (36, 46), electrons stored in the floating gate (28) of at least one desired memory cell may be discharged.
Inventors
- 👤 Masashi Wada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 20:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
311 words
An electrically erasable and programmable read only memory device (10) including a one-chip semiconductive substrate (12) of one conductivity type and a plurality of memory cells (14) arranged on said substrate (12) in a matrix form, characterized in that each memory cell of said plurality of memory cells (14) comprises a floating gate (28) insulated from said substrate (12); a first electrode layer (36, 60) which is insulated from said substrate (12) and said floating gate (28) and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; a second electrode layer (46, 62) which is insulated from said substrate (12), said floating gate (28), and said first electrode layer (36, 60) and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; and a third electrode layer (32) which is connected to one of diffusion layers (24, 26), which is insulated from said substrate (12), said floating gate (28), said first electrode layer (36, 60) and the second electrode layers (46, 62), and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; whereby a voltage of a first potential is applied to said first electrode layer (36, 60) and said second electrode layer (46, 62), and a voltage of a second potential is applied to said third electrode layer (32) so that carriers are charged into said floating gate (28) from said diffusion layer (26) which is connected to said third electrode layer (32) in at least one of said memory cells (14), and the voltage of the second potential is applied to said first electrode layer (36, 60) and said second electrode layer (46, 62), and the voltage of the first potential is applied to said third electrode layer (32) so that carriers are discharged from said floating gate (28) of at least one of said memory cells (14).
Claim 2
Dependent Claim
311 words
An electrically erasable and programmable read only memory device (10) including a one-chip semiconductive substrate (12) of one conductivity type and a plurality of memory cells (14) arranged on said substrate (12) in a matrix form, characterized in that each memory cell of said plurality of memory cells (14) comprises a floating gate (28) insulated from said substrate (12); a first electrode layer (36, 60) which is insulated from said substrate (12) and said floating gate (28) and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; a second electrode layer (46, 62) which is insulated from said substrate (12), said floating gate (28), and said first electrode layer (36, 60) and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; and a third electrode layer (32) which is connected to one of diffusion layers (24, 26), which is insulated from said substrate (12), said floating gate (28), said first electrode layer (36, 60) and the second electrode layers (46, 62), and which is capacitively coupled to said floating gate (28) at a predetermined capacitance; whereby a voltage of a first potential is applied to said first electrode layer (36, 60) and said second electrode layer (46, 62), and a voltage of a second potential is applied to said third electrode layer (32) so that carriers are charged into said floating gate (28) from said diffusion layer (26) which is connected to said third electrode layer (32) in at least one of said memory cells (14), and the voltage of the second potential is applied to said first electrode layer (36, 60) and said second electrode layer (46, 62), and the voltage of the first potential is applied to said third electrode layer (32) so that carriers are discharged from said floating gate (28) of at least one of said memory cells (14).
Claim 3
Dependent Claim
48 words
A device according to claim 1, characterized in that said capacitance (C CF1 ) between said floating gate (28) and said first electrode layer (36, 60) is substantially the same as said capacitance (C CF2 ) between said floating gate (28) and said second electrode layer (46, 62).
Claim 4
Dependent Claim
64 words
A device according to claim 2, characterized in that said capacitance (C E ) between said floating gate (28) and said third electrode layer (32) is set to be smaller than said capacitance (CCF1) between said floating gate (28) and said first electrode layer (36, 60) and said capacitance (C CF2 ) between said floating gate (28) and said second electrode layer (46, 62).
Claim 5
Dependent Claim
76 words
A device according to claim 1, characterized in that said floating gate (28) has a first gate portion (28-1) overlying said channel region (30) defined by said diffusion layers (24, 26) and extending in a predetermined first direction, and a second gate portion (28-2) extending from an end portion of said first gate portion (28-1) in a second direction perpendicular to the first direction so that said floating gate (28) is of L-shape as a whole.
Claim 6
Dependent Claim
31 words
A device according to claim 4, characterized in that said diffusion layers (24, 26) have an increased impurity concentration of the opposite conductivity type and, correspond respectively to source and drain.
Claim 7
Dependent Claim
32 words
A device according to claim 4, characterized in that said first electrode layer (36, 60) overlies said first gate portion (28-1) of said floating gate (28) and extends in the first direction.
Claim 8
Dependent Claim
32 words
A device according to claim 4, characterized in that said third electrode layer (32) extends substantially parallel to the first direction and has a projection layer (34) projecting in the second direction.
Claim 9
Dependent Claim
39 words
A device according to claim 6 or 7, characterized in that said projecting layer (34) of said electrode layer (32) underlies a region corresponding to said end portion of said first gate portion (28-1) of said floating gate (28).
Claim 10
Dependent Claim
61 words
A device according to claim 1, characterized in that each memory cell of said plurality of memory cells (14) arranged on said substrate (12) in the matrix form substantially comprises a metal oxide semiconductor transistor, said transistor comprising said diffusion layers (24, 26), said first electrode layer (36, 60), said second electrode layer (46, 62) and said third electrode layer (32).
Claim 11
Dependent Claim
68 words
A device according to claim 9, characterized in that said first electrode layers (36, 60) of memory cells aligned in the same row among said memory cells (14) are commonly connected to a row line (16), so that a voltage of a potential substantially the same as one of the first and second potentials is applied to said first electrode layers (36, 60) through said row line (16).
Claim 12
Dependent Claim
67 words
A device according to claim 9, characterized in that said second electrode layers (46, 62) of memory cells aligned in the same column among said memory cells is commonly connected to a column line (19), so that a voltage of a potential substantially the same as one of the first and second potentials is applied to said second electrode layers (46, 62) through said column line (19).
Claim 13
Dependent Claim
52 words
A device according to claim 9, characterized in that said third electrode layers (32) formed on said memory cells (14) is supplied with a voltage of a potential substantially the same as one of the first potential or the second potential in response to mode selection between data writing and data erasure.
References Cited (Backward Citations)
US3728695A
Cited
DE2643947A1
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.