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EP0060198A2
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Serial-parallel-serial charge coupled device and method of transferring charge therein
Assignee: Fairchild Semiconductor Corp
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Filing: 1982-03-08
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Granted: —
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Expires: 2002-03-08
Abstract
Abstract An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.
Inventors
- 👤 Kalyanasundaram Venkateswaran
- 👤 Ramesh C. Varshney
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 15:38
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/287; H; H10; H10D; H10D84/00; H10D84/891
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
119 words
A two phase serial-parallel-serial charge-coupled device memory array, including means for transferring charge from parallel registers to a serial output register characterized by a first transfer gate associated with each first alternate parallel register, a second transfer gate associated with each second alternate parallel register, a first storage gate associated with each first transfer gate, a second storage gate associated with each second transfer gate, and means for controlling said first transfer gates and said second transfer gates whereby charge from said first alternate parallel registers is transferred through said first storage gates to said serial output register and then charge from said second alternate parallel registers is transferred through said second storage gates to said serial output register.
Claim 2
Dependent Claim
119 words
A two phase serial-parallel-serial charge-coupled device memory array, including means for transferring charge from parallel registers to a serial output register characterized by a first transfer gate associated with each first alternate parallel register, a second transfer gate associated with each second alternate parallel register, a first storage gate associated with each first transfer gate, a second storage gate associated with each second transfer gate, and means for controlling said first transfer gates and said second transfer gates whereby charge from said first alternate parallel registers is transferred through said first storage gates to said serial output register and then charge from said second alternate parallel registers is transferred through said second storage gates to said serial output register.
Claim 3
Dependent Claim
38 words
Means for transferring charge as defined by Claim 1 characterized in that said first and second transfer gates are linearaly offset to prevent concurrent charge transfer from said first alternate parallel registers and said second alternate parallel registers.
Claim 4
Dependent Claim
41 words
Means for transferring charge as defined by Claim 1 or 2 and further characterized by a third storage gate means for receiving charge from said first storage gates and said second storage gates and transferring charge to said output serial register.
Claim 5
Dependent Claim
31 words
Means for transferring charge as defined by Claim 3 characterized in that said third storage gate means includes a separate storage gate for each of said first and second storage gates.
Claim 6
Dependent Claim
76 words
Means for transferring charge as defined by any one of Claims 1-4 characterized by a third storage gate associated and shared with each first storage gate and each second storage gate whereby charge from a first storage gate and from a second storage gate are alternately loaded into said third storage gate, and in that said means for controlling said first transfer gates and said second transfer gates is responsive to a serial register clock signal.
Claim 7
Independent Claim
78 words
A method of transferring charge from parallel registers to a serial output register of a two phase serial-parallel-serial charge-coupled device memory array characterized by the steps of: a) transferring charge from first alternate parallel registers to first storage gates, b) transferring charge from said first storage gates to said serial output register; c) transferring charge from second alternate parallel register to second storage gates; and d) transferring charge from said second storage gates to said serial output register.
Claim 8
Independent Claim
78 words
A method of transferring charge from parallel registers to a serial output register of a two phase serial-parallel-serial charge-coupled device memory array characterized by the steps of: a) transferring charge from first alternate parallel registers to first storage gates, b) transferring charge from said first storage gates to said serial output register; c) transferring charge from second alternate parallel register to second storage gates; and d) transferring charge from said second storage gates to said serial output register.
Claim 9
Dependent Claim
40 words
The method of transferring charge as defined by Claim 6 characterized in that steps b) and d) include transferring charge from said first storage gates and said second storage gates through third storage gate means to said serial output register.
Claim 10
Dependent Claim
91 words
The method of Claim 6 characterized in that step b includes transferring said charge from said first storage gates to shared storage gates; transferring said charge from said shared storage gates to said serial output register in response to a clock signal of said serial output register; and in that step d) includes transferring said charge from said second storage gates to said shared storage gates; and transferring said charge from said third storage gates to said serial output register in response to a clock signal of said serial output register.
Claim 11
Dependent Claim
67 words
9 . The method of transferring charge as defined by Claim 8 characterized in that each of said shared storage gates alternately receives first charge from a first storage gate and second charge from a second storage gate and alternately transfers said first charge and said second charge to a storage gate of said serial output register in response to clock signals of said serial output register.
Claim 12
Dependent Claim
143 words
A two phase serial-parallel-serial charge-coupled device array, including charge transfer means characterized by a first endmost storage element of a first parallel register; a second endmost storage element of a second parallel register; a first transfer element associated with said first endmost storage element; a second transfer element associated with said second endmost storage element; a first intermediate storage element associated with said first transfer element; a second intermediate storage element associated with said second transfer element; and a common storage element associated with said first and second intermediate storage elements whereby charge from said first endmost storage element is transferred through said first transfer element and said first intermediate storage element to said common storage element, and then charge from said second endmost storage element is transferred through said second transfer element and said second intermediate storage element to said common element.
Claim 13
Dependent Claim
143 words
A two phase serial-parallel-serial charge-coupled device array, including charge transfer means characterized by a first endmost storage element of a first parallel register; a second endmost storage element of a second parallel register; a first transfer element associated with said first endmost storage element; a second transfer element associated with said second endmost storage element; a first intermediate storage element associated with said first transfer element; a second intermediate storage element associated with said second transfer element; and a common storage element associated with said first and second intermediate storage elements whereby charge from said first endmost storage element is transferred through said first transfer element and said first intermediate storage element to said common storage element, and then charge from said second endmost storage element is transferred through said second transfer element and said second intermediate storage element to said common element.
Claim 14
Dependent Claim
69 words
Charge transfer means as defined by Claim 10 characterized in that said common storage element is associated with a storage element of an output serial register whereby charge from said first endmost storage element and charge from said second endmost element are alternately transferred from said common'storage element - to said storage element of said output serial register in response to a clock signal of said output serial register.
References Cited (Backward Citations)
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