Patent EP0059848A2 successfully refreshed from Google Patents.
EP0059848A2
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EP
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FET and method for manufacturing such
Assignee: International Business Machines Corp
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Filing: 1982-02-10
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Granted: —
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Expires: 2002-02-10
Abstract
Abstract A field effect transistor and method of making the same are disclosed. A thick mesa (17) of dielectric material is grown on a semiconductor substrate (10) and two or more layers (20a, b; 28a, b) of polycrystalline silicon grown on the vertical sides of the mesa (17) serve a masking function to define the gate region of the transistor with high accuracy. The mesa (17) and the two or more polycrystalline layers (20a, b; 28a, b) remain in the final device.
Inventors
- 👤 Ven Young Doo
- 👤 Paul Jamin Tsang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/01; H10D30/021; H10D30/0221; H10D30/028; H10D30/601; H10D30/603; H10D30/605; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
A method of forming a field effect transistor comprising the following steps: a) providing a semiconductor substrate (10) of one conductivity type having a shallow surface layer (16) of opposite conductivity type; b) forming a thick mesa (17) of dielectric material on said substrate (10); c) forming a first layer (20a, b) of polycrystalline silicon only on the vertical surfaces of said mesa (17); d) introducing one or more impurities into said substrate (10), said mesa (17) and said first layer (16) of polycrystalline silicon masking said substrate (10) against the introduction of said impurities; e) forming a second layer (28a, b) of polycrystalline silicon only on the vertical surfaces of said first layer (20a, b) of polycrystalline silicon; f) introducing one or more impurities of a different conductivity type from said first impurities into said substrate (10) at areas other than those masked by said mesa (17).
Claim 2
Independent Claim
148 words
A method of forming a field effect transistor comprising the following steps: a) providing a semiconductor substrate (10) of one conductivity type having a shallow surface layer (16) of opposite conductivity type; b) forming a thick mesa (17) of dielectric material on said substrate (10); c) forming a first layer (20a, b) of polycrystalline silicon only on the vertical surfaces of said mesa (17); d) introducing one or more impurities into said substrate (10), said mesa (17) and said first layer (16) of polycrystalline silicon masking said substrate (10) against the introduction of said impurities; e) forming a second layer (28a, b) of polycrystalline silicon only on the vertical surfaces of said first layer (20a, b) of polycrystalline silicon; f) introducing one or more impurities of a different conductivity type from said first impurities into said substrate (10) at areas other than those masked by said mesa (17).
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein said first silicon layer and said second polycrystalline silicon layers (20a, b; 28a, b) form the gate of said transistor.
Claim 4
Dependent Claim
36 words
The method of claim 1, further comprising forming an annular layer (14) of dielectric isolation on said substrate around said mesa (17), thereby producing a defined area between said mesa (17) and said annular layer (14).
Claim 5
Dependent Claim
21 words
The method of claim 3, wherein the one or more impurities introduced in step d) are introduced into said defined area.
Claim 6
Dependent Claim
73 words
The method of claim 4, wherein a portion of said defined area is masked subsequent to introducing the one or more impurities in step d) but prior to the forming of said second layer (28a, b) of polycrystalline silicon in step e) and wherein one or more impurities of a conductivity type opposite the conductivity type of the impurities introduced in step d) are introduced into the unmasked portion of said defined area.
Claim 7
Dependent Claim
131 words
FET comprising a semiconductor substrate (10) with source and drain regions (29, 32a; 26 32b) spaced apart by a channel (30) and formed at one surface of the semiconductor substrate (10) and an insulating film (14) overlying said source and drain regions, characterized by a thick vertically oriented mesa (17) of silicon oxide on the insulating film (14) in the area between said channel and drain region (26, 32b), a lightly doped region (16) of the same conductivity type as said drain region underneath said mesa extending from said drain to said channel, a dual layer (20a, 28a) structure on the vertical surfaces of the mesa (17) comprising an inner polysilicon layer (20a) and an outer polysilicon layer (28a), and a gate region (30) only under the outer polysilicon layer (20a).
Claim 8
Dependent Claim
131 words
FET comprising a semiconductor substrate (10) with source and drain regions (29, 32a; 26 32b) spaced apart by a channel (30) and formed at one surface of the semiconductor substrate (10) and an insulating film (14) overlying said source and drain regions, characterized by a thick vertically oriented mesa (17) of silicon oxide on the insulating film (14) in the area between said channel and drain region (26, 32b), a lightly doped region (16) of the same conductivity type as said drain region underneath said mesa extending from said drain to said channel, a dual layer (20a, 28a) structure on the vertical surfaces of the mesa (17) comprising an inner polysilicon layer (20a) and an outer polysilicon layer (28a), and a gate region (30) only under the outer polysilicon layer (20a).
References Cited (Backward Citations)
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