EP0059810A1 — Microprogrammed digital data processing system em…

Claim 1

Independent Claim 279 words

In a microprogrammed data processing system providing for the concurrent execution of a plurality of tasks, the combination comprising: program control means for generating a plurality of tasks, each task being performable by the execution of one or more task microinstructions; microinstruction storage means for storing selectably addressable task microinstructions for use in performing said tasks; task control means coupled to said program control means for activating a plurality of said tasks and for selectively addressing said microinstruction storage means in order to provide for execution of the activated tasks; microinstruction execution means for concurrently executing task microinstructions selected from said microinstruction storage means in a multi-phased staged manner; microinstruction sequencing control means responsive to microinstructions selected from said microinstruction storage means and to the results of microinstruction execution performed by said microinstruction execution means for providing indications to said task control means for use in determining the selective addressing of said microinstruction storage means; said microinstruction sequencing control means also being operative to provide a subroutine entry indication and a task identification indication when a task arrives at the beginning of a subroutine and a subroutine return indication and a task identification indication when the task arrives at the end of a subroutine; and subroutine control means operating in a multi-phased staged manner in synchronism with said microinstruction execution means, said subroutine control means being responsive to said subroutine entry and return indications and to said task identification indications for determining and storing multiple levels of return addresses for each task during performance of a subroutine thereby and for providing an appropriate return address to said sequencing control means when a task reaches the end of a subroutine.

Claim 2

Dependent Claim 279 words

In a microprogrammed data processing system providing for the concurrent execution of a plurality of tasks, the combination comprising: program control means for generating a plurality of tasks, each task being performable by the execution of one or more task microinstructions; microinstruction storage means for storing selectably addressable task microinstructions for use in performing said tasks; task control means coupled to said program control means for activating a plurality of said tasks and for selectively addressing said microinstruction storage means in order to provide for execution of the activated tasks; microinstruction execution means for concurrently executing task microinstructions selected from said microinstruction storage means in a multi-phased staged manner; microinstruction sequencing control means responsive to microinstructions selected from said microinstruction storage means and to the results of microinstruction execution performed by said microinstruction execution means for providing indications to said task control means for use in determining the selective addressing of said microinstruction storage means; said microinstruction sequencing control means also being operative to provide a subroutine entry indication and a task identification indication when a task arrives at the beginning of a subroutine and a subroutine return indication and a task identification indication when the task arrives at the end of a subroutine; and subroutine control means operating in a multi-phased staged manner in synchronism with said microinstruction execution means, said subroutine control means being responsive to said subroutine entry and return indications and to said task identification indications for determining and storing multiple levels of return addresses for each task during performance of a subroutine thereby and for providing an appropriate return address to said sequencing control means when a task reaches the end of a subroutine.

Claim 3

Dependent Claim 67 words

The invention in accordance with claim 1, wherein each of said microinstruction execution means and said subroutine control means operates so that its operations with respect to a task microinstruction are performed in a plurality of stages occurring over a plurality of time periods, and so that during each time period the operations required for a plurality of stages are performable with respect to a different task.

Claim 4

Dependent Claim 37 words

The invention in accordance with claim 2, wherein each of said microinstruction means and said subroutine control means provides the same number of stages and time periods for performing its operations with respect to a task microinstruction.

Claim 5

Dependent Claim 44 words

The invention in accordance with claim 1, wherein said task control means provides for addressing said microinstruction storage means in a manner so as to permit the execution of task microinstructions in an intermixed order regardless of the particular task to which each belongs.

Claim 6

Dependent Claim 119 words

The invention in accordance with-claim 1, 2, 3 or.4, wherein said microinstruction execution means provides for execution of a task microinstruction in a plurality of at least three stages including a read operation stage, a compute operation stage, and a write operation stage, each stage requiring one time period, wherein during each time period a write operation is performable with respect to a first task microinstruction, a compute operation is performable with respect to a second task microinstruction, and a read operation is performable with respect to a third task microinstruction, and wherein said subroutine control means provides the same number-of stages and time periods for performing its operations with respect to a task microinstruction-as does-said microinstruction control means.-

Claim 7

Dependent Claim 98 words

The invention in accordance with claim 5, wherein said subroutine control means comprises: a return address storage means for each task; and return address control means responsive to said subroutine entry and task identification indications for determining a return address and for storing this return address in the return address storage means of the identified task; and said return address control means being responsive to said subroutine return and task identification indications for causing the most recent return address stored in the return-address storage means.-of the identified task-to be accessed therefrom and applied to said sequencing control means.

Claim 8

Dependent Claim 50 words

The invention in accordance with claim 6, wherein said return address control means is operable during each time period to permit a return address to be determined for a first task concurrently with the storing of a return address for a second task in its respective return -address storage means.

Claim 9

Dependent Claim 80 words

The invention in accordance with claim 7, wherein said return address control means is also operable during each time period to permit a most recent return address for a third task to be accessed from its respective return address storage means for transfer to said sequencing control means concurrently with the determining of a return address for said first task and concurrently with the storing of a return address for said second task in its respective return address storage means.

Claim 10

Dependent Claim 68 words

The invention in accordance with claim 8, wherein said return address control means provides for the determining of a return address in response to a subroutine entry indication of an identified task during a first one of said stages and provides for the storing of this determined return address in the respective return address storage means of the same identified task during a second one of said stages.

Claim 11

Dependent Claim 179 words

The invention in accordance with claim 6, wherein said return address storage means includes a first storage means for each.task for storing a plurality.of return addresses for its respective task and a second significantly faster storage means for each task for storing the most recent address of its respective task, wherein said return address control means operates in'response to said subroutine entry and task identification indications for causing the determined return address to be stored in both of the respective first and storage means of the identified task, wherein said return address control means operates in response to said subroutine return and task identification indications to access the most recent return address from the second storage means of the identified task for transfer- to said system, and wherein said return address control means also operates in response to said subroutine return and task identification indications for causing the next most recent return address to be accessed from the respective first storage means of the identified task and to be stored in the second storage means of the identified task.

Claim 12

Dependent Claim 139 words

The invention in accordance with claim 10, wherein the first storage means of each task comprises a stack for storing a plurality of return addresses, wherein a stack level pointer register is provided for each stack for storing a stack level pointer indicative of the number of return addresses stored in its respective stack, wherein the second return address storage means of each task comprises a fast access register, wherein said control means operates to store a return address in a stack at a level indicated by its respective stack level pointer, wherein said control means operates in response to said entry and return ind idations to maintain the stack level pointers correctly updafed, and wherein said control means accesses the next most recent return address from a stack at the level indicated by the respective stack level pointer.

Claim 13

Dependent Claim 68 words

The invention in accordance with Claim 11, wherein said return address control means includes means responsive to a task identification indication provided by said system for accessing from the respective stack level pointer register the respective stack level pointer value for the identified task for use by said first control means in storing a return address at the appropriate level of the stack corresponding to the identified task.

Claim 14

Dependent Claim 217 words

. - The invention in accordance with claim 1, 2, 3 or 4, wherein said subroutine control means comprises: a first return address storage means for each task for storing return addresses for the respective task during performance of a subroutine thereby; a second return address storage means for each task for storing the most recent return address of the respective task, said second return address storage means providing for significantly faster access than said first return address means; first control means responsive to said subroutine entry and task -identification indications for determining a return address for -the indicated subroutine and for storing this return address in both of the - respective -first and second return address registers of the task; second control means responsive to said subroutine return - and task identification indications for causing the most recent return address stored in the respective second return address storage means of the identified task to be accessed and transferred to said sequencing control means; and third control means also responsive to said subroutine return and task identification indications for causing the next most recent return address to be accessed from the respective first return address storage means of the identified task and to be stored in the respective second return address storage means of the identified task.

Microprogrammed digital data processing system employing multiphase subroutine control for concurrently executing tasks

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