Patent EP0057111A2 successfully refreshed from Google Patents.
EP0057111A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Read only memory
Assignee: Arris Technology Inc
•
Filing: 1982-01-28
•
Granted: —
•
Expires: 2002-01-28
Abstract
Abstract A read only memory is provided in which the memory cells (24) are single metal gate or silicon gate field effect transistors (26). Each FET (26) has one of several different thresholds or states. The size or area of the FET gates (64) at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instance. The output of a cell is fed to several flip-flops (42,44,46), which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder (48) converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128k on a single chip.
Inventors
- 👤 Kenneth Leslie Naiff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:36
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C11/5692
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
101 words
A read only memory comprising a plurality of multi-state cells interconnected in a ROM matrix, each of said cells having substantially the same surface dimensions, and having one of at least three possible states; means for selecting a particular one of said cells to be read; means for applying to a selected cell, an input signal varying in amplitude with time for stimulating an output signal from said cell in accordance with the state of said cell, said output signal being of one of at least two possible amplitude levels; and circuit means for receiving the output from said selected cell.
Claim 2
Dependent Claim
101 words
A read only memory comprising a plurality of multi-state cells interconnected in a ROM matrix, each of said cells having substantially the same surface dimensions, and having one of at least three possible states; means for selecting a particular one of said cells to be read; means for applying to a selected cell, an input signal varying in amplitude with time for stimulating an output signal from said cell in accordance with the state of said cell, said output signal being of one of at least two possible amplitude levels; and circuit means for receiving the output from said selected cell.
Claim 3
Dependent Claim
31 words
A read only memory according to claim 1, wherein said input signal varies slowly with time, and said output signal is displaced in time depending upon the state of said cell.
Claim 4
Dependent Claim
85 words
A read only memory according to claim 2 wherein each cell has one of at least four states; three of said states are gate threshold levels responsive to different amplitudes of said input signal,,and the fourth state is not operable by said input signal; said cell being switched at a different instant of time during the application of said input signal if in one of said first three states, and not being switched at all by said applied ramp signal if having said fourth state.
Claim 5
Dependent Claim
30 words
A read only memory according to claim 3 wherein the cell has a FET structure with a gate region having different degrees of doping corresponding to said three different states.
Claim 6
Dependent Claim
67 words
A read only memory according to claim 1, 2 3 or 4 , wherein one of said states causes said cell to remain unchanged during reading, and said output signal from said cells in said one state being of one amplitude level; and the output signals from said cells in the other states being the other amplitude level and displaced in time in accordance with their state.
Claim 7
Dependent Claim
115 words
A read only memory according to claim 5, further comprising at least three reference circuits connected to receive said input signal, each of said circuits having a different one of said cells in the other states, and providing said time displaced output signal of said other amplitude in accordance with the state of said circuits; at least three flip-flops each having two inputs and an output, said first inputs being connected to the output of said at least three reference circuits respectively, and the second inputs being connected to receive the output of the cell being read; each of said flip-flops providing an output signal in accordance with coincidence of signals at its two inputs.
Claim 8
Dependent Claim
37 words
A read only memory in accordance with claim 6 further comprising an encoder connected to receive the output from the three flip-flops and providing a two bit binary signal in accordance with the output from the flip-flops.
Claim 9
Dependent Claim
28 words
A read only memory according to claim 6 further comprising a delay circuit between at least one of said reference circuits and the input to its corresponding flip-flop.
Claim 10
Dependent Claim
29 words
A read only memory according to claim 1, wherein said input signal is a step signal, and said output signals are currents proportional to the states of said cells.
Claim 11
Dependent Claim
48 words
A read only memory according to claim 9, wherein each cell has one of at least four states; three of said states are gate threshold levels providing respectively said different amplitudes of current flow when gated on, and the fourth state is not operable by said input signal.
Claim 12
Dependent Claim
30 words
A read only memory according to claim 10 wherein the cell has a FET structure with a gate region having different degrees of doping corresponding to said three different states.
Claim 13
Dependent Claim
63 words
A read only memory according to claim 1, 9, 10 or 11, wherein one of said states causes said cell to remain unchanged during reading, and said output signal from said cells in said one state being of one amplitude level; and the output signals from said cells in the other states being of different current amplitude levels in accordance with their states.
Claim 14
Dependent Claim
113 words
A read only memory according to claim 12 further comprising three reference circuits connected to receive said input signal, each of said circuits having a different one of said cells in the other states, and providing said output signals of said different current amplitudes respectively in accordance with the states of said circuits; at least three comparison circuits each having two inputs and an output, said first inputs being connected to the output of said three reference circuits respectively, and the second inputs being connected to receive the output of the cell being read; each of said comparison circuits providing an output signal in accordance with coincidence of signals at its two inputs.
Claim 15
Dependent Claim
39 words
A read only memory in accordance with claim 13 further comprising an encoder connected to receive the output from the three comparison circuits and providing a two bit binary signal in accordance with the output from the comparison circuits.
Claim 16
Dependent Claim
32 words
6 or 15. A read only memory according to claim/13 wherein said referenced circuits comprise three cells having FETs with substantially the same surface dimension as the cells in the ROM matrix.
Claim 17
Dependent Claim
78 words
6 or 16. A read only memory according to claim/13, wherein said multistate cells in the ROM matrix each comprise a FET having a gate region with different gate doping corresponding to said three threshold levels, and said three re 7 ference circuits each comprise a FET, at least one of which has one of said different gate doping of said matrix FETs, and a substantially different gate surface dimension than the corresponding FET cell in the matrix.
Claim 18
Dependent Claim
32 words
A read only memory according to claim 16, wherein at least two of said three reference circuits have FETs with surface gate dimensions different from those of the FETs in said matrix.
Claim 19
Dependent Claim
67 words
A read only memory in accordance with claim 17, wherein one of said reference cells FET is an enhancement mode, and with the same gate dimension as the FETs in the matrix; said second reference circuit FET being of the enhancement mode and with a larger surface gate, and said third reference circuit FET being of the intermediate threshold level and having a larger surface gate region.
Claim 20
Dependent Claim
90 words
A read only memory array comprising a plurality of cells each of said cells being a field effect transistor and each having a gate region of substantially the same surface area and shape; a first portion of said FETs being enhancement mode devices, a second and different portion of said FETs being depletion mode devices; a third and different portion of said FETs having a gate region doping intermediate to that of the enhancement and depletion mode devices; and a portion of said FET devices being inoperable as a FET.
Claim 21
Dependent Claim
90 words
A read only memory array comprising a plurality of cells each of said cells being a field effect transistor and each having a gate region of substantially the same surface area and shape; a first portion of said FETs being enhancement mode devices, a second and different portion of said FETs being depletion mode devices; a third and different portion of said FETs having a gate region doping intermediate to that of the enhancement and depletion mode devices; and a portion of said FET devices being inoperable as a FET.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.