Patent EP0056895A2 successfully refreshed from Google Patents.
EP0056895A2
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EP
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Automatic test system
Assignee: Westinghouse Electric Corp
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Filing: 1981-09-16
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Granted: —
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Expires: 2001-09-16
Abstract
Abstract An automatic test system controlled by a general purpose digital central processor (20) is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices (24,26,30) via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor (44) which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix (28) also communicates with the digital processor (20) to connect the appropriate test device to the unit under test.
Inventors
- 👤 Raymond Allen Lloyd
- 👤 Larry Lee Charles
- 👤 William Francis Susie
- 👤 Jr. Allen Wesley Tate
- 👤 James Richard Reeder
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 20:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31907; G01R31/2832; G01R31/2834; G01R31/3183; G01R31/318342; G01R31/31912; G01R31/31917; G01R31/31926; G06; G06F; G06F2201/00; G06F2201/865
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
An automatic test system for supplying test signals to apparatus to be tested and for evaluating the response of said apparatus to said test signals, comprising in combination: a central programmable digital processor (20) for accepting test programs in a first high level language, said program comprising a plurality of program sequences each specifying a test to be performed on a unit under test (41); a plurality of test devices (24, 26, 30) coupled to communicate with said digital processor via a first data bus; a switch matrix (28) coupled to receive switching commands from said general purpose processor via a second data bus to control the flow of test signals from said test device to apparatus to be tested characterized in that said central programmed digital processor utilizes a compiler language; each of said test devices comprising an interface unit (34) to couple said central digital processor to said first data bus to receive a test program; an interface digital processor (44) coupled to receive data via said first data bus; and a test instrument (40) coupled to receive instructions from said interface processor (44) via a third data bus and in response thereto perform the test specified thereby, each sequence of said program in said first high level language to said interface digital processor (44) specifying a test being compacted by said interface digital processor to produce said compact version of said first high level language test program for use by said test instrument.
Claim 2
Dependent Claim
246 words
An automatic test system for supplying test signals to apparatus to be tested and for evaluating the response of said apparatus to said test signals, comprising in combination: a central programmable digital processor (20) for accepting test programs in a first high level language, said program comprising a plurality of program sequences each specifying a test to be performed on a unit under test (41); a plurality of test devices (24, 26, 30) coupled to communicate with said digital processor via a first data bus; a switch matrix (28) coupled to receive switching commands from said general purpose processor via a second data bus to control the flow of test signals from said test device to apparatus to be tested characterized in that said central programmed digital processor utilizes a compiler language; each of said test devices comprising an interface unit (34) to couple said central digital processor to said first data bus to receive a test program; an interface digital processor (44) coupled to receive data via said first data bus; and a test instrument (40) coupled to receive instructions from said interface processor (44) via a third data bus and in response thereto perform the test specified thereby, each sequence of said program in said first high level language to said interface digital processor (44) specifying a test being compacted by said interface digital processor to produce said compact version of said first high level language test program for use by said test instrument.
Claim 3
Dependent Claim
21 words
An automatic test device in accordance with claim 1 wherein said interface processor includes a read only memory for storing programs.
Claim 4
Dependent Claim
22 words
An automatic test device in accordance with claim 1 or 2 wherein said interface processor includes a read/write memory for data processing.
Claim 5
Dependent Claim
18 words
An automatic test device in accordance with claim 3 wherein said read/write memory is a random access memory.
Claim 6
Dependent Claim
52 words
An automatic test system in accordance with any of the preceding claims wherein each of said interface digital processors is coupled to said central processor to selectively receive instructions from said central processor and in response thereto perform test specified thereby and couple the results of said test to said central processor.
Claim 7
Dependent Claim
40 words
An automatic test system in accordance with claim 5 wherein said switching matrix includes a programmable interface processor for receiving instructions from said central processor and in response thereto coupling one of said test devices to apparatus to be tested.
References Cited (Backward Citations)
No citation records indexed.
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