Abstract In a high-speed external memory system which is equipped with a program node for controlling a read/write operation of an internal control register and a memory of the external memory system by a central processing unit and a direct memory access mode permitting a direct access to a main memory, there are provided first and second location address registers. The memory address is performed by the first location address register in the direct memory access mode and by the second location address register in the program mode, whereby it is made possible to execute the read/write operation of the memory of the external memory system in the program mode during burst timing while in data transfer in the direct memory access mode, thus permitting high-efficiency data processing.
A high-speed external memory system which is equipped with a program mode for controlling a read/write operation of an internal control register and a memory of the external memory system by a central processing unit and a direct memory access mode permitting a direct access to a main memory, char- acterized in that first and second location address registers are provided, and memory addressing is performed by the first location address register in the direct memory access mode and by the second location address register in the program mode, whereby the read/write operation of the memory of the external memory system can be executed by the central processing unit in the program mode while in the execution of data processing.
Claim 2
Dependent Claim
120 words
A high-speed external memory system which is equipped with a program mode for controlling a read/write operation of an internal control register and a memory of the external memory system by a central processing unit and a direct memory access mode permitting a direct access to a main memory, char- acterized in that first and second location address registers are provided, and memory addressing is performed by the first location address register in the direct memory access mode and by the second location address register in the program mode, whereby the read/write operation of the memory of the external memory system can be executed by the central processing unit in the program mode while in the execution of data processing.
Claim 3
Dependent Claim
92 words
A high-speed external memory system according to claim 1 wherein the first location address register and/or the second location address register comprises a block address register for storing a block address and a location address register for storing a location address; and the block address and high-order bits of the location address are provided from the block address register and the location address register first and then low-order bits of the location address register are provided from the location address register, thereby to perform the memory addressing on a time shared basis.
Claim 4
Dependent Claim
32 words
A high-speed external memory system according to claim 1 or 2 wherein the first and second location address registers are provided for the direct memory access mode and the program mode, respectively.
Claim 5
Dependent Claim
49 words
A high-speed external memory system according to claim 1 or 2 wherein a memory controller for switching between the selection of the first location address register in the direct memory access mode and the selection of the second location address register in the program mode is constituted by decoders.
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