Ghost reduction circuit arrangement for a television receiver

Claim 1

A ghost reduction circuit arrangement for a television receiver comprising: a) an input terminal (100') to which a television signal containing ghost signal is applied; b) a first set of delay elements of n (111' - 114') each with a first delay time ( T '), which are connected in series, with the input terminal connecting to said input terminal (100'); c) a circuit (103) for generating a reference signal on the basis of said television signal, said circuit being connected to said input terminal; d) a first comparing circuit (104') for comparing said television signal with said reference signal; e) a first set of gain controllable circuits (121' - 124') of n for controlling the amplitude and the polarity of the output signals of said delay elements, to which the output signals from said first set of delay elements (111'-114') are applied, respectively; f) a gain control voltage generating circuit (102') for controlling gains (a l , a 2 , ... an) of said gain controllable circuits (121' - 124') and their output signals, on the basis of the output signal from said first comparing circuit (104'); g) a first adder circuit (105') for adding the output signals from said first set of gain controllable circuits (121' - 124'); h) a first subtractor circuit (106') for subtracting an output signal of said first adder from said television signal supplied through said input terminal (100'); i) a second set of delay elements (211 - 214) of m each with a second delay time (r") connected in series; j) a delay signal selection switch (403) for selectively supplying the output signals of said first set of delay elements to the input terminal of said second set of delay elements; k) a switch control circuit (402) for controlling said delay signal selection switch (403) on the basis of an output signal voltage from said gain control voltage generating circuit (102'); ℓ) a second comparing circuit (203) for comparing said reference signal with said first subtractor circuit (106'); m) a second set of gain controllable circuits (220 - 224) of m for controlling the amplitudes and the polarity of the output signals from said second set of delay elements provided corresponding to said second set of delay elements; n) a second control voltage generating circuit (201) for supplying a signal voltage for controlling the gains (b o , b l , ... b ) and the polarity of said second set of gain controllable circuits to said second set of gain controllable circuits (201), on the basis of the output signal from said second comparing circuit (203); o) a second adder circuit (204) for adding the output signals of said second set of gain control circuits; and p) a second adder (204) for subtracting the output signal of said second adder circuit (204) from the output signal from said first subtractor (106').