Patent EP0055347A2 successfully refreshed from Google Patents.
EP0055347A2
Expired / Lapsed
EP
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DC stable memory
Assignee: International Business Machines Corp
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Filing: 1981-10-20
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Granted: —
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Expires: 2001-10-20
Abstract
Abstract A single device DC stable memory cell is arranged in a fully selectable static memory and adapted to have simplified reading and writing operations for either one of two information states. Each cell has a pair of word lines (WL1, WL2), an SCR latch comprising an NPN device (11) and associated parasitic PNP device (10) connected between each pair of word lines (WL1, WL2). Interface means for reading and writing include means (12,13) coupling first and second information state regardless of its pre-existing state in response to selective alteration of the voltage states in said bit and word lines. Means coupled to one of the bit lines and to the latch establish a distinctive current level for the one bit line in response to selective alteration of the voltage state of at least one word line (BL1 or BL2). An integrated resistor-Schottky (R"12) combination turns off the parasitic PNP to prevent accidental (noise related) switch-over to the "on" state. Each cell can be enclosed in a single isolated region in an integrated device.
Inventors
- 👤 Shashi Dhar Malaviya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
145 words
A fully selectable static memory cell , including an SCR latch, comprising an NPN device (11) and an associated quasi-parasitic PNP (10) device, connected between a pair of word lines (WL1, WL2), capable of writing either one of two information states or reading either one of two information states, comprising: interface means (12-14, 16-23, 25) in said cell and coupled to said SCR latch for reading and writing, said interface means writing a first or second information state regardless of the pre-existing state of said latch by selective alteration of potentials on said word lines (WL1. WL2), and on two connected bit lines (BL1, BL2) and establishing a distinctive current level in said one of said bit lines (BL1 or BL2), in response to selective alterations of potentials on at least one word line (WLl or WL2), indicative of the information state of said latch.
Claim 2
Dependent Claim
145 words
A fully selectable static memory cell , including an SCR latch, comprising an NPN device (11) and an associated quasi-parasitic PNP (10) device, connected between a pair of word lines (WL1, WL2), capable of writing either one of two information states or reading either one of two information states, comprising: interface means (12-14, 16-23, 25) in said cell and coupled to said SCR latch for reading and writing, said interface means writing a first or second information state regardless of the pre-existing state of said latch by selective alteration of potentials on said word lines (WL1. WL2), and on two connected bit lines (BL1, BL2) and establishing a distinctive current level in said one of said bit lines (BL1 or BL2), in response to selective alterations of potentials on at least one word line (WLl or WL2), indicative of the information state of said latch.
Claim 3
Dependent Claim
28 words
The static memory cell of Claim 1 which further includes noise margin improvement means coupling said SCR latch to one or another of said word lines (WLl, WL2).
Claim 4
Dependent Claim
29 words
The static memory cell of Claim 1 which further includes noise margin improvement means including a Schottky diode coupled between said SCR latch and one of said word lines.
Claim 5
Dependent Claim
31 words
The static memory cell of Claim 2 or 3 in which said noise margin improvement means includes a P-type Schottky diode coupled between base and emitter of said NPN device (11).
Claim 6
Dependent Claim
30 words
The static memory cell of Claim 2 or 3 in which said noise margin improvement means comprises an N-type Schottky diode coupled between base and emitter of said PNP device(10).
Claim 7
Dependent Claim
55 words
The static memory cell of Claim 1 in which said interface means includes NPN interface transistor means (13) with collector in common with said NPN device (11) and connected to one of said bit lines (BL1, BL2), for initiating conduction in said SCR latch in response to a selected potential on said bit line (BL2).
Claim 8
Dependent Claim
36 words
The static memory cell of Claim 6 wherein said NPN interface transistor means (13) has a P-type base coupled to said bit line (BL2) and N-type emitter coupled to a one of said word lines (BL2).
Claim 9
Dependent Claim
34 words
The static memory cell of Claim 6 in which said interface transistor means (13) has a P-type base coupled to said NPN device emitter and an emitter coupled to said bit line (WLl, WL2).
Claim 10
Dependent Claim
36 words
The static memory cell of Claim 6 in which said NPN interface transistor means (13) has an emitter coupled to said bit line (BL2) and a base coupled to one of said word lines (WL1, WL2).
Claim 11
Dependent Claim
68 words
The static memory cell of Claim 6 in which said interface means includes a second NPN transistor means, said second NPN transistor means having a collector and base regions in common with said NPN device (11) and a separate emitter coupled to another (BL1) of said bit lines for sensing the status of said SCR latch in response to predetermined potential on said another of said bit lines.
Claim 12
Dependent Claim
57 words
The static memory cell of Claim 1 wherein said interface means includes an N-type Schottky diode (12) coupled between said SCR latch and a one of said bit lines (BL1), whereby current is drawn from said bit line (BLl) if said word line (WL1) is controlled in potential and said SCR latch is in an "on" state.
Claim 13
Dependent Claim
47 words
The static memory cell of Claim 1 in which said interface means includes a P-type Schottky diode (14) coupled between another of said bit lines (BL2) and.a base of said NPN device (11), whereby conduction of said P-type Schottky diode (14) terminates conduction in said SCR latch.
Claim 14
Dependent Claim
46 words
The static memory cell of Claim 11 in which said interface means includes NPN interface transistor means coupled to another of said bit lines for initiating conduction of said SCR latch in response to a predetermined potential on said another of said bit lines (BL1, BL2).
Claim 15
Dependent Claim
62 words
The static memory cell of Claim 1 in which said interface means includes NPN transistor means with collector and base regions in common with regions of said PNP device (16) and an emitter coupled to one of said bit lines (BLI, BL2) for initiating said SCR latch into conduction in response to a predetermined potential on said one of said bit lines.
Claim 16
Dependent Claim
30 words
The static memory cell of Claim 14 in which said interface means includes an N-type Schottky diode coupled between another of said bit lines and collector of said NPN device.
Claim 17
Dependent Claim
33 words
The static memory cell of Claim 14 in which said interface means includes a P-type Schottky diode coupled between a base region of said NPN device and said another of said bit lines.
Claim 18
Dependent Claim
33 words
The static memory cell of Claim 14 in which said interface means includes a second NPN device (16) with collector and base regions in common with said NPN device and an emitter coupled
Claim 19
Dependent Claim
70 words
. 18. The static memory cell of Claim 11 in which said interface means further includes an NPN transistor (17) with emitter coupled to said one of said bit lines (BL2), base coupled to one of said word lines (WLl) and collector in common with said NPN device collector, and, a P-type Schottky (12) diode coupled between another of said bit lines (BL1) and base of said NPN device (10).
Claim 20
Dependent Claim
80 words
The static memory cell of Claim 1 in which said inter- . face means includes PNP and NPN interface transistors (23, 25), said PNP interface transistor (23) with emitter connected to another of said bit lines (BL2) and collector common to said PNP device collector, said NPN interface transistor (25) with emitter connected to one of said word lines (WL2), base connected to said one of said bit lines (BL1) and collector common with the collector of said NPN device.
Claim 21
Dependent Claim
25 words
The static memory cell of Claim 19 which further includes an anti-saturation clamp (SDI) connected between base and collector of said NPN interface transistor (25).
Claim 22
Dependent Claim
171 words
A fully selectable static memory cell capable of writing either one of two information states or reading either one of two information states and contained within a single isolated region comprising: a substrate supporting a P-type semiconductor, means for isolating a region of said semiconductor, an N sub-collector within said isolated region, a first NPN transistor within said region including said sub-collector a P-type NPN base region and an N-type NPN emitter region, a parasitic PNP transistor within said region, said parasitic PNP transistor including a base region comprising said NPN collector and a collector region comprising said NPN base region, controllable word and bit lines in said isolated region and coupling means for coupling said word and bit lines to said first and second transistors for operating said transistors as an SCR latch to read the information state of said latch or to write either of said information states regardless of the pre-existing state of said latch in response to read and write signals on said word and bit lines.
Claim 23
Dependent Claim
171 words
A fully selectable static memory cell capable of writing either one of two information states or reading either one of two information states and contained within a single isolated region comprising: a substrate supporting a P-type semiconductor, means for isolating a region of said semiconductor, an N sub-collector within said isolated region, a first NPN transistor within said region including said sub-collector a P-type NPN base region and an N-type NPN emitter region, a parasitic PNP transistor within said region, said parasitic PNP transistor including a base region comprising said NPN collector and a collector region comprising said NPN base region, controllable word and bit lines in said isolated region and coupling means for coupling said word and bit lines to said first and second transistors for operating said transistors as an SCR latch to read the information state of said latch or to write either of said information states regardless of the pre-existing state of said latch in response to read and write signals on said word and bit lines.
Claim 24
Dependent Claim
69 words
The static memory cell of Claim 21 in which said means coupling said word and bit lines to said transistor includes a further N-type region diffused within a further P-type region diffused in said N-type NPN collector, and means coupling one of said bit lines to said further P-type region for initiating conduction in said SCR latch in response to predetermined potential on said one of said bit lines.
Claim 25
Dependent Claim
33 words
The static memory cell of Claim 22 in which said coupling means includes an N-type Schottky diode (12) comprising said NPN collector region and a metal contact comprising another of said bit lines.
Claim 26
Dependent Claim
55 words
The static memory cell of Claim 21 in which said coupling means includes a P-type Schottky diode (14) comprising a one of said bit lines, said NPN collector region and a P-type implant in said NPN collector region, and an N-type Schottky diode (12) comprising another of said bit lines and said NPN collector region.
Claim 27
Dependent Claim
69 words
The static memory cell of Claim 21 in which said means coupling said word and bit lines to said transistor includes a further N-type region diffused with a further P-type region diffused in said N-type NPN collector, and means coupling one of said bit lines to said fur-' ther N-type region for initiating conduction in-said SCR latch in response to predetermined potential on said one of said bit lines.
Claim 28
Dependent Claim
31 words
The static memory cell of Claim 25 in which said means coupling includes a second N-type emitter region associated with said NPN transistor and coupled to another of said bit lines.
Claim 29
Dependent Claim
30 words
The static memory cell of Claim 25 in which said means coupling further includes an N-type Schottky diode (12) comprising another of said bit lines and said NPN .collector region.
Claim 30
Dependent Claim
41 words
The static memory cell-of Claim 21 in which said means coupling includes a second N-type region which is diffused in a P-type region comprising an emitter of said PNP transistor, said second N-type region coupled to one of said bit lines.
Claim 31
Dependent Claim
29 words
The static memory cell of Claim 28 in which said means coupling includes an N-type Schottky diode (12) comprising another of said bit lines and said NPN collector region.
Claim 32
Dependent Claim
33 words
The static memory cell of Claim 29 in which said means coupling includes a P-type Schottky diode (14) comprising a base region of said NPN transistor and said another of said bit lines.
Claim 33
Dependent Claim
35 words
The static memory cell of Claim 28 in which said means coupling includes a third N-type region associated with said NPN transistor and comprising a second emitter and connected to another of said bit lines.
Claim 34
Dependent Claim
90 words
The static memory cell of Claim 21 in which said coupling means includes a second NPN transistor coupled to a first bit line and a second PNP transistor coupled to a second bit line, said second NPN transistor comprising a further N-type region in a further P-type region in said NPN collector, and means for connecting said first bit line to said further P-type region, said second PNP transistor comprising another P-type region in said NPN collector, and means for connecting said second bit line to said another P-type region.
Claim 35
Dependent Claim
20 words
The static memory cell of Claim 32 which further includes an anti-saturation clamp (SDI) connected to said second NPN transistor.
References Cited (Backward Citations)
No citation records indexed.
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