Patent EP0053075A2 successfully refreshed from Google Patents.
EP0053075A2
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Nonvolatile memory
Assignee: Fujitsu Ltd
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Filing: 1981-11-20
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Granted: —
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Expires: 2001-11-20
Abstract
Abstract A nonvolatile memory, especially an electrically erasable and programmable read only memory (EE-PROM) is disclosed. In each of the memory cells (MC) comprising the EE-PROM, four transistors are formed, that is a read transistor (Q 11 ) and a first selecting transistor (Q 21 ), both connected in series, and a write-erase transistor (Q 12 ) and a -:second selecting transistor (0 22 ), both connected in series, the write-erase transistor has a floating gate (FG) being provided with, partially, a thin insulation layer thereunder, the read transistor also has a floating gate (FG) being provided with a thick insulation layer thereunder, the first and second selecting transistors are turned to ON or OFF together.
Inventors
- 👤 Arakawa Hideki
- 👤 Higuchi Mitsuo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 18:56
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
244 words
A nonvolatile memory comprising a plurality of memory cells (MC , MC b ) and a plurality of column lines (Y a ,Y b ), row lines (X a ,X b ) and program lines (PR a ,PR b ) which cooperate with the memory cells, each of the memory cells is comprised of a selecting transistor (Q 2 ) and a programming transistor (Q 1 ), both connected in series, the programming transistor including a control gate (CG) and a floating gate (FG), the selecting transistor is connected, at its drain (D), to the column line (Y) and, at its gate (G), to the row line (X), the programming transistor (Q 1 ) is connected, at its control gate (CG), to the program line (PR) characterized in that, in each of said memory cells, the selecting transistor is divided into two transistors of a first selecting transistor (Q 21 ) and a second selecting transistor (Q 22 ), the programming transistor is divided into two transistors of a read transistor (Q 11 ) having a floating gate (FG) provided with a relatively thick insulation layer thereunder, and a write-erase transistor (Q 12 ) having a floating gate (FG) provided with, partially, a relatively thin insulation layer thereunder, the first selecting transistor (Q 21 ) and the read transistor (Q ) are connected in series, also the second selecting transistor (Q 22 ) and the write-erase transistor (Q 12 ) are connected in series.
Claim 2
Dependent Claim
244 words
A nonvolatile memory comprising a plurality of memory cells (MC , MC b ) and a plurality of column lines (Y a ,Y b ), row lines (X a ,X b ) and program lines (PR a ,PR b ) which cooperate with the memory cells, each of the memory cells is comprised of a selecting transistor (Q 2 ) and a programming transistor (Q 1 ), both connected in series, the programming transistor including a control gate (CG) and a floating gate (FG), the selecting transistor is connected, at its drain (D), to the column line (Y) and, at its gate (G), to the row line (X), the programming transistor (Q 1 ) is connected, at its control gate (CG), to the program line (PR) characterized in that, in each of said memory cells, the selecting transistor is divided into two transistors of a first selecting transistor (Q 21 ) and a second selecting transistor (Q 22 ), the programming transistor is divided into two transistors of a read transistor (Q 11 ) having a floating gate (FG) provided with a relatively thick insulation layer thereunder, and a write-erase transistor (Q 12 ) having a floating gate (FG) provided with, partially, a relatively thin insulation layer thereunder, the first selecting transistor (Q 21 ) and the read transistor (Q ) are connected in series, also the second selecting transistor (Q 22 ) and the write-erase transistor (Q 12 ) are connected in series.
Claim 3
Dependent Claim
96 words
A nonvolatile memory as set forth in claim 1, wherein said first and second selecting transistors and said read and write-erase transistors are formed in and on a semiconductor substrate, the semiconductor substrate contains a U-shaped diffusion area therein, electrically connected to said column line, so as to form drains and sources of the above four transistors, both said first selecting transistor and said read transistor are formed on and along one side of said U-shaped area and both said second selecting transistor and said write-erase transistor are formed on and along the other side thereof.
Claim 4
Dependent Claim
45 words
A nonvolatile memory as set forth in claim 2, wherein both said first and second selecting transistors are located close to the bottom side of said U-shaped diffusion area and both said read and write-erase transistors are located close to the upper open ends thereof.
Claim 5
Dependent Claim
73 words
A nonvolatile memory as set forth in claim 3, wherein both the gates of said first and second selecting transistors connect, at respective cross portions, with said row line which is arranged perpendicular to said column line, both the control gates of said write-erase transistor and said read transistor connect at respective cross portions, with a sub-part of said program line, the program line part is arranged in parallel with said row line.
Claim 6
Dependent Claim
27 words
1 5. A nonvolatile memory as set forth in claim 4, wherein a major part of said program line is arranged in parallel with said column line.
Claim 7
Dependent Claim
28 words
A nonvolatile memory as set forth in claim 5, wherein said diffusion area for comprising the drains and sources of said four transistors have n T- type conductivity.
Claim 8
Dependent Claim
25 words
A nonvolatile memory as set forth in claim 6, wherein a channel formed between the drain and source of said write-erase transistor has n-type conductivity.
Claim 9
Dependent Claim
99 words
A nonvolatile memory as set forth in claim 1, wherein, in each of said memory cells, said program line is divided into a first program line and a second program line, said first and second selecting transistors being further provided with a third selecting transistor cooperating with the second selecting transistor as one body, the control gates of the read and write-erase transistors are coupled with the first program line and the second program line is coupled with the gate of the third selecting transistor, the second program line is activated only when the corresponding memory cell is selected.
Claim 10
Dependent Claim
98 words
A nonvolatile memory as set forth in claim 8, wherein said first, second and third selecting transistors and said read and write-erase transistors are formed in and on a semiconductor substrate, the semiconductor substrate contains a U-shaped diffusion area therein, electrically connected to said column line, so as to form drains and sources of the above five transistors, both said first selecting transistor and said read transistor are formed on and along one side of said U-shaped area and said second and third selecting transistors and said write-erase transistor are formed on and along the other side thereof.
Claim 11
Dependent Claim
45 words
A nonvolatile memory as set forth in claim 9, wherein said first, second and third selecting transistors are located close to the bottom side of said U-shaped diffusion area and both said read and write-erase transistors are located close to the upper open ends thereof.
Claim 12
Dependent Claim
87 words
A nonvolatile memory as set forth in claim 10, wherein both the gates of said first and second selecting transistors connect, at respective cross portions, with said row line which is arranged perpendicular to said column line, both the control gates of said write-erase transistor and said read transistor connect at respective cross portions, with said first program line, the first program line is arranged in parallel with said row line, the second program line is arranged perpendicular to both said row line and first program line.
Claim 13
Dependent Claim
28 words
A nonvolatile memory as set forth in claim 11, wherein said second program line is arranged in parallel with and inside both sides of said U-shaped diffusion area.
References Cited (Backward Citations)
No citation records indexed.
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