Patent EP0052828A2 successfully refreshed from Google Patents.
EP0052828A2
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Microprocessor System
Assignee: Texas Instruments Inc
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Filing: 1981-11-10
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Granted: —
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Expires: 2001-11-10
Abstract
Abstract A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The ALU, registers and busses along with the control ROM are constructed in an interrelated layout whereby minimum space is needed on the chip. Like bits in all registers and the ALU are aligned and in a regular pattern. The busses are metal lines overlying each of the strips of ALU/register bits. Controls are polysilicon lines perpendicular to the busses and aligned with columns of the control ROM. The control ROM is an array of rows and columns of potential MOS transistors, compressed by eliminating column lines which contain no transistors. The number of bits per column is a minimum to enhance compressability producing a wide configuration (long row lines) which allows the columns for control signals to align with the part of the ALU/register strip where the signal is to be used. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.
Inventors
- 👤 Kevin C. Mcdonough
- 👤 Karl M. Guttag
- 👤 Gerald E. Laws
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 01:11
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/30156; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F9/22; G06F9/223; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
206 words
A microprocessor system comprising: a memory containing a plurality of locations defined by a given set of addresses and containing program instructions and data, input/output means for receiving and transmitting information, a central processing unit connected to said memory and said input/output means by conductor means to couple addresses, program instructions, data and information between the memory, input/output means and central processing means, said central processing unit comprising: an arithmetic logic unit for performing arithmetic - and logic operations on data, a plurality of registers for containing address and data, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set, control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, and an auxilliary storage unit containing a plurality of locations defined by a second set of addresses which may contain program instruction, wherein the second set may overlap said given set of addresses, with means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 2
Dependent Claim
206 words
A microprocessor system comprising: a memory containing a plurality of locations defined by a given set of addresses and containing program instructions and data, input/output means for receiving and transmitting information, a central processing unit connected to said memory and said input/output means by conductor means to couple addresses, program instructions, data and information between the memory, input/output means and central processing means, said central processing unit comprising: an arithmetic logic unit for performing arithmetic - and logic operations on data, a plurality of registers for containing address and data, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set, control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, and an auxilliary storage unit containing a plurality of locations defined by a second set of addresses which may contain program instruction, wherein the second set may overlap said given set of addresses, with means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 3
Dependent Claim
23 words
A system according to claim 1 wherein said auxilliary storage unit is on a single semiconductor integrated circuit with said central processing unit..
Claim 4
Dependent Claim
15 words
A system according to claim 2 wherein said memory is not on said integrated circuit.
Claim 5
Dependent Claim
24 words
A system according to claim 3 wherein said auxilliary storage unit and said memory are activated for memory fetch in the alternative or interleaved.
Claim 6
Dependent Claim
35 words
A system according to claim 3 wherein said given set of addresses defines a memory map limited by the logic address space allowed by the number of bits of addresses coupled by said conductor means,
Claim 7
Dependent Claim
166 words
A microprocessor comprising: a main memory containing a plurality of locations defined by an address space, a central processing unit in a semiconducotr unit separate from said main memory, said central processing unit including an arithmetic logic unit, a plurality of registers, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set as stored in said main memory, and control means responsive to the program instruction of said instruction set in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, an auxilliary storage unit containing a plurality of locations defined by a first set of addresses not within said address space, wherein the first set may overlap said address space, and means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 8
Dependent Claim
166 words
A microprocessor comprising: a main memory containing a plurality of locations defined by an address space, a central processing unit in a semiconducotr unit separate from said main memory, said central processing unit including an arithmetic logic unit, a plurality of registers, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set as stored in said main memory, and control means responsive to the program instruction of said instruction set in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, an auxilliary storage unit containing a plurality of locations defined by a first set of addresses not within said address space, wherein the first set may overlap said address space, and means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 9
Dependent Claim
22 words
Apparatus according to claim 6 wherein said auxilliary storage unit is on a single semiconductor integrated circuit with said central processing unit.
Claim 10
Dependent Claim
203 words
A microprocessor comprising: a main memory containing a.plurality of locations defined by an address space, a central processing unit in a semiconductor unit separate from said main memory, said central processing unit including an arithmetic logic unit, a plurality of registers, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set as stored in said main memory, and control means responsive to the program instruction of said instruction set in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, a first auxilliar y storage unit containing a plurality of locations defined by a first set of addresses not within said address space, wherein the first set may overlap said address space, a separate second auxilliary storage unit containing a plurality of locations defined by a second set of addresses not within said address space, wherein the - second set may overlap said address space, and means initiated by the control means for transferring sequences of program instructions from such first or second storage units to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 11
Dependent Claim
203 words
A microprocessor comprising: a main memory containing a.plurality of locations defined by an address space, a central processing unit in a semiconductor unit separate from said main memory, said central processing unit including an arithmetic logic unit, a plurality of registers, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined instruction set as stored in said main memory, and control means responsive to the program instruction of said instruction set in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, a first auxilliar y storage unit containing a plurality of locations defined by a first set of addresses not within said address space, wherein the first set may overlap said address space, a separate second auxilliary storage unit containing a plurality of locations defined by a second set of addresses not within said address space, wherein the - second set may overlap said address space, and means initiated by the control means for transferring sequences of program instructions from such first or second storage units to said instruction register in response to predetermined program instructions, such sequences being of said instruction set.
Claim 12
Dependent Claim
59 words
Apparatus according to claim 8 wherein said first auxiliary storage unit is on a single semiconductor integrated circuit with said central processing unit, wherein said main memory is not on said integrated circuit, wherein said second auxiliary storage unit is not on said integrated circuit, and wherein said first and second auxiliary storage units are activated in the alternative.
Claim 13
Dependent Claim
261 words
A microprocessor system comprising: a first memory containing a plurality of locations with a first set of addresses defining a first memory map, the first memory containing program instructions and data. input/output means for receiving and transmitting information, a central processing unit connected to said first memory and said input/output means by conductor means to couple address, program instruction, data and information between the memory, input/output means and central processing means, said central processing unit comprising: an arithmetic logic unit for performing arithmetic and logic operations on data, a plurality of registers for containing address and data, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined.instruction set. control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, an auxiliary storage unit containing a plurality of locations with a second set of addresses defining a second memory map, wherein the second.set may overlap said given set of addresses but is not part of said first memory map, with addressing means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set, and a second memory containing a plurality of locations with a third set of addresses not within said second memory map, said addressing means transferring sequences of program instructions.from said second memory to said instruction register for addresses within the third set.
Claim 14
Dependent Claim
261 words
A microprocessor system comprising: a first memory containing a plurality of locations with a first set of addresses defining a first memory map, the first memory containing program instructions and data. input/output means for receiving and transmitting information, a central processing unit connected to said first memory and said input/output means by conductor means to couple address, program instruction, data and information between the memory, input/output means and central processing means, said central processing unit comprising: an arithmetic logic unit for performing arithmetic and logic operations on data, a plurality of registers for containing address and data, an instruction register for receiving program instructions for execution by the central processing unit, such program instructions being of a predetermined.instruction set. control means responsive to the program instruction in said instruction register to produce a plurality of controls for defining the operation of the central processing unit, an auxiliary storage unit containing a plurality of locations with a second set of addresses defining a second memory map, wherein the second.set may overlap said given set of addresses but is not part of said first memory map, with addressing means initiated by the control means for transferring sequences of program instructions from such storage unit to said instruction register in response to predetermined program instructions, such sequences being of said instruction set, and a second memory containing a plurality of locations with a third set of addresses not within said second memory map, said addressing means transferring sequences of program instructions.from said second memory to said instruction register for addresses within the third set.
Claim 15
Dependent Claim
52 words
A system according to claim 10 wherein said auxilliary storage unit is on a single semiconductor.integrated circuit with said central processing unit, wherein said first memory and said second memory are not on said integrated circuit, and/or wherein said first auxiliary storage unit and said second memory are accessed in the alternative.
Claim 16
Dependent Claim
18 words
Apparatus according to claim 11 wherein said first auxiliary storage unit is deactivated when accessing the second memory.
Claim 17
Dependent Claim
29 words
Apparatus according to claim 11 wherein said first memory map is limited by the-logical address space allowed by the number of bits of addresses coupled by said conductor means.
Claim 18
Dependent Claim
202 words
A microprocessor comprising: an arithmetic logic unit containing N parallel bits with each bit having two inputs and an output, the bits of the arithmetic logic unit being formed in a face of a semiconductor body in a regular linear pattern. a plurality of separate registers, each containing N parallel bits, each bit having an input and an output, the bits of the registers being.formed in said face in a regular pattern matched with the bits of the arithmetic logic unit, a plurality.of separate parallel busses, each having N bits, each formed at said face and running in a substantially straight pattern generally perpendicular to the linear-pattern of the bits of the arithmetic logic unit aid registers, each of the busses intersecting each bit of the arithmetic logic unit and a plurality of said registers, a plurality of control lines at said face running generally perpendicular to said busses and parallel to the linear pattern of the arithmetic logic unit and registers, the control lines being connected to logic means in the arithmetic logic unit and registers to define connections to and from the busses for the inputs and outputs of the registers and inputs and outputs of the arithmetic logic unit.
Claim 19
Dependent Claim
202 words
A microprocessor comprising: an arithmetic logic unit containing N parallel bits with each bit having two inputs and an output, the bits of the arithmetic logic unit being formed in a face of a semiconductor body in a regular linear pattern. a plurality of separate registers, each containing N parallel bits, each bit having an input and an output, the bits of the registers being.formed in said face in a regular pattern matched with the bits of the arithmetic logic unit, a plurality.of separate parallel busses, each having N bits, each formed at said face and running in a substantially straight pattern generally perpendicular to the linear-pattern of the bits of the arithmetic logic unit aid registers, each of the busses intersecting each bit of the arithmetic logic unit and a plurality of said registers, a plurality of control lines at said face running generally perpendicular to said busses and parallel to the linear pattern of the arithmetic logic unit and registers, the control lines being connected to logic means in the arithmetic logic unit and registers to define connections to and from the busses for the inputs and outputs of the registers and inputs and outputs of the arithmetic logic unit.
Claim 20
Dependent Claim
68 words
A device according to claim 14 wherein: said control lines are conductors extending along said face insulated therefrom and forming gates of insulated gate field effect transistors of said logic means; busses are conductors extending along said face above said control lines insulated therefrom; and/or said control lines are polycrystalline silicon and busses are metal; . and the registers include an instruction register and a program counter register.
Claim 21
Dependent Claim
308 words
A microprocessor comprising: an airthmetic logic unit containing N parallel bits with each bit having two inputs and an output, the bits of the arithmetic logic unit being formed in a face of a semiconductor body in a regular linear pattern, a plurality of separate registers, each containing N parallel bits, each bit having an input and an output, the bits of the registers being formed in said face in a regular pattern matched with the bits of the arithmetic - logic unit, a plurality of separate parallel busses, each having N bits, each formed at said face and running in a substantailly straight pattern generally perpendicular to the linear pattern of the bits of the arithmetic logic unit and registers, each of the busses intersecting each bit of the arithmetic logic unit and a plurality of said registers, = a plurality of control lines at said face running generally perpendicular to said busses and parallel to the linear pattern of the arithmetic logic unit and registers, the control lines being connected to logic means in the arithmetic logic unit and registers to define connections to and from the busses for the inputs and outputs of the registers and inputs and output of the arithmetic logic unit, and a logic array for generating a plurality of control signals on said control lines device comprising: a plurality of row lines and means for selecting one of said row lines for activation in response to an address, a plurality of column lines intercepting said row lines to provide an array, the column lines divided into a plurality of separate groups with one. group for each of said control lines- and means for selecting no more than one column lines in each group for activation in response to an address,. the number of column lines per group differing among the groups.
Claim 22
Dependent Claim
308 words
A microprocessor comprising: an airthmetic logic unit containing N parallel bits with each bit having two inputs and an output, the bits of the arithmetic logic unit being formed in a face of a semiconductor body in a regular linear pattern, a plurality of separate registers, each containing N parallel bits, each bit having an input and an output, the bits of the registers being formed in said face in a regular pattern matched with the bits of the arithmetic - logic unit, a plurality of separate parallel busses, each having N bits, each formed at said face and running in a substantailly straight pattern generally perpendicular to the linear pattern of the bits of the arithmetic logic unit and registers, each of the busses intersecting each bit of the arithmetic logic unit and a plurality of said registers, = a plurality of control lines at said face running generally perpendicular to said busses and parallel to the linear pattern of the arithmetic logic unit and registers, the control lines being connected to logic means in the arithmetic logic unit and registers to define connections to and from the busses for the inputs and outputs of the registers and inputs and output of the arithmetic logic unit, and a logic array for generating a plurality of control signals on said control lines device comprising: a plurality of row lines and means for selecting one of said row lines for activation in response to an address, a plurality of column lines intercepting said row lines to provide an array, the column lines divided into a plurality of separate groups with one. group for each of said control lines- and means for selecting no more than one column lines in each group for activation in response to an address,. the number of column lines per group differing among the groups.
Claim 23
Dependent Claim
70 words
A microprocessor according to claim 16 wherein: a potential cell is provided at the intersection of row line and each column line in:said logic array; the potential cells include insulated gate field effect transistors; there is at least one cell on each column line in each group; and the means for selecting column lines activates a column line in some but not all of said groups for a given address.
Claim 24
Dependent Claim
44 words
A microprocessor according to claim 17 wherein: said control lines are conductors extending along said face insulated therefrom and forming gates of insulated gate field effect transistors of said logic means; said busses are conductors-extending along said face above said control lines insulated therefrom.
Claim 25
Dependent Claim
106 words
A system according to claim 16 wherein: the logic array means includes two decode arrays, one on each side of the regular pattern of ALU and registers; in each of the decode arrays the columns are parallel to the control lines and positioned in approximate alignment with the logic means in the ALU and registers where the control signal is utilized; and the decode arrays are much wider in a direction perpendicular to the columns. than the length of the columns, and wherein the width of the decode arrays matches the size of the pattern of ALU and registers in a direction parallel with the busses.
Claim 26
Dependent Claim
77 words
A decoder comprising: an array of potential cells with M rows and N columns, first selector means for activating one of said M rows as defined by an address of B bits, second selector means for selecting one of said N columns as defined by an address of C bits, where M equals 2 , and wherein logically unneeded columns of potential cells are omitted from the array, whereby N is much less than 2 C ,
Claim 27
Dependent Claim
77 words
A decoder comprising: an array of potential cells with M rows and N columns, first selector means for activating one of said M rows as defined by an address of B bits, second selector means for selecting one of said N columns as defined by an address of C bits, where M equals 2 , and wherein logically unneeded columns of potential cells are omitted from the array, whereby N is much less than 2 C ,
Claim 28
Dependent Claim
31 words
A decoder according to claim 20 wherein: the potential cells are field effect transistors; the second selector means is an array of 2 C rows and N columns said potentail cells.
Claim 29
Dependent Claim
99 words
A logic array for generating a plurality of control signals for a microprocessor device comprising: a plurality of row lines and means for selecting one of said row lines for activation in response to an address, a plurality of column lines intercepting said row lines to provide an array, the column lines divided into a plurality of separate groups with one group for each of said control signals and means for selecting no more than one column line in each group for activation in response to an address, the number of column lines per group differing among the groups.
Claim 30
Dependent Claim
99 words
A logic array for generating a plurality of control signals for a microprocessor device comprising: a plurality of row lines and means for selecting one of said row lines for activation in response to an address, a plurality of column lines intercepting said row lines to provide an array, the column lines divided into a plurality of separate groups with one group for each of said control signals and means for selecting no more than one column line in each group for activation in response to an address, the number of column lines per group differing among the groups.
Claim 31
Dependent Claim
95 words
A logic array according to claim 22 wherein: a potential cell is provided at the intersection of each row line and each column line; wherein the potential cells are insulated gate field effect transistors; wherein there is at least one cell on each column line in each group; wherein the means for selecting column lines activates a column line in some but not all of said groups for a given address; and/or wherein the maximum number of column lines in a group does not exceed N and said given address contains C bits, where N=2c.
Claim 32
Independent Claim
106 words
A method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor device comprising the seps of: defining a plurality of equal groups of said columns one group for.each control signal, the columns intercepting said rows at said potential cells, providing row select means for activiting one row in response to a first address, providing column select means for activating no more than one column in each group in response to a second address, eliminating columns which contain no cells for a given sequence of control signals to be generated for the microprocessor device.
Claim 33
Independent Claim
106 words
A method of making a logic array of rows and columns of potential cells for generating a plurality of control signals for a microprocessor device comprising the seps of: defining a plurality of equal groups of said columns one group for.each control signal, the columns intercepting said rows at said potential cells, providing row select means for activiting one row in response to a first address, providing column select means for activating no more than one column in each group in response to a second address, eliminating columns which contain no cells for a given sequence of control signals to be generated for the microprocessor device.
Claim 34
Dependent Claim
131 words
A method according to claim 24: including the step of eliminating parts of said column select means for the columns containing no cells; wherein some of the groups contain unequal numbers of columns after eliminating the columns which contain no cells; including the step of forming an insulated gate field effect transistor at the location of each one of the potential cells for which a control signal is to be generated for a given first and second address; wherein said addresses-are selected to maximize the number of columns containing no cells; including the step of populating the array with cells using false logic-to thereby increase the number of columns containing no cells; and/or including the step of inverting said control signals to thereby increase the number of columns containing no cells.
Claim 35
Dependent Claim
151 words
A microprocessor system comprising: a memory containing a large number of locations defined by address and containing program instructions and data, input/output means for receiving and transmitting information, a central processing unit formed in a single integrated circuit connected to said memory and said input/output means by conductor means to couple addresses, program instruction, data and information between the memory, input/output means and central processing means, logic array means in said central processing unit for receiving representations of said program instructions for decoding and generating control signals to define operation of the system, the logic array means including, a plurality of rows and columns of potential cells, the columns arranged in a plurality of groups corresponding to the control signals with means to select rows and columns in response to a program instruction, the number of columns per group differing among the groups and all columns having at least one cell.
Claim 36
Dependent Claim
151 words
A microprocessor system comprising: a memory containing a large number of locations defined by address and containing program instructions and data, input/output means for receiving and transmitting information, a central processing unit formed in a single integrated circuit connected to said memory and said input/output means by conductor means to couple addresses, program instruction, data and information between the memory, input/output means and central processing means, logic array means in said central processing unit for receiving representations of said program instructions for decoding and generating control signals to define operation of the system, the logic array means including, a plurality of rows and columns of potential cells, the columns arranged in a plurality of groups corresponding to the control signals with means to select rows and columns in response to a program instruction, the number of columns per group differing among the groups and all columns having at least one cell.
References Cited (Backward Citations)
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