Patent EP0052450A1 successfully refreshed from Google Patents.
EP0052450A1
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EP
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Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes
Assignee: Fujitsu Ltd
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Filing: 1981-10-29
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Granted: —
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Expires: 2001-10-29
Abstract
Abstract An integrated circuit comprising at least one bipolar transistor (I) and at least one MIS FET (II) in a single semiconductor substrate (1) has an electrode for each region (2, 16, 31) of the bipolar transistor and each region (17, 18) of the MIS FET, which electrode comprises a polycrystalline semiconductor layer (28) and a metal layer (34-42) and has the same conduction type as the corresponding region and is connected by ohmic contact with the surface of the corresponding region. The method involves forming a polycrystalline semiconductor layer both over the emitter window of the bipolar transistor and on the gate insulating film (20) of the MIS FET, thus protecting the latter during the diffusion process used to from the emitter (31).
Inventors
- 👤 Yoshinobu Momma
- 👤 Tsuneo Funatsu
- 👤 Atusi Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 12:08
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
121 words
'A semiconductor device comprising at least one bipolar transistor (1) and at least one MIS FET (II) integrated in a single semiconductor substrate (1), characterised in that in each region of the emitter (31), base (16) and collector (2) of the bipolar transistor and in each region of the source (17) and drain (18) of the MIS FET there is provided an electrode which comprises a polycrystal semiconductor layer (28) and an electrode metal layer (34-42) upon the polycrystal semiconductor layer, the polycrystal layer (28) in each said region .(2, 16, 17, 18, 31) having the same conduction type as the corresponding underlying region to form an ohmic contact between the electrode metal layer and the surface of the corresponding region.
Claim 2
Dependent Claim
121 words
'A semiconductor device comprising at least one bipolar transistor (1) and at least one MIS FET (II) integrated in a single semiconductor substrate (1), characterised in that in each region of the emitter (31), base (16) and collector (2) of the bipolar transistor and in each region of the source (17) and drain (18) of the MIS FET there is provided an electrode which comprises a polycrystal semiconductor layer (28) and an electrode metal layer (34-42) upon the polycrystal semiconductor layer, the polycrystal layer (28) in each said region .(2, 16, 17, 18, 31) having the same conduction type as the corresponding underlying region to form an ohmic contact between the electrode metal layer and the surface of the corresponding region.
Claim 3
Independent Claim
168 words
A method of manufacturing a semiconductor device having at least one bipolar transistor (I) and-at least one MIS FET (II) integrated in a single semiconductor substrate (1), comprising process steps of: forming a base region (16) of the bipolar transistor and a source region (17) and a drain region (18) of the MIS FET in the semiconductor substrate, forming a gate insulating film (8) of the MIS FET on the semiconductor substrate, and then forming an emitter region (31) of the bipolar transistor in the substrate; characterised in that the method also comprises process steps of: after forming the gate insulating film (8) on the surface of the substrate and providing at least a window (22) for forming the emitter region of the bipolar transistor, forming a polycrystal semiconductor layer (28) covering at least the emitter window of the bipolar transistor and the gate insulating film; and introducing an impurity through the emitter window (22) into the substrate to form the emitter region (31) of the bipolar transistor.
Claim 4
Independent Claim
168 words
A method of manufacturing a semiconductor device having at least one bipolar transistor (I) and-at least one MIS FET (II) integrated in a single semiconductor substrate (1), comprising process steps of: forming a base region (16) of the bipolar transistor and a source region (17) and a drain region (18) of the MIS FET in the semiconductor substrate, forming a gate insulating film (8) of the MIS FET on the semiconductor substrate, and then forming an emitter region (31) of the bipolar transistor in the substrate; characterised in that the method also comprises process steps of: after forming the gate insulating film (8) on the surface of the substrate and providing at least a window (22) for forming the emitter region of the bipolar transistor, forming a polycrystal semiconductor layer (28) covering at least the emitter window of the bipolar transistor and the gate insulating film; and introducing an impurity through the emitter window (22) into the substrate to form the emitter region (31) of the bipolar transistor.
References Cited (Backward Citations)
GB2011173A
Cited
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