Patent US1451401A successfully refreshed from Google Patents.
Patent EP0052432A2 successfully refreshed from Google Patents.
EP0052432A2
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Digital signal processing
Assignee: Sony Corp
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Filing: 1981-10-20
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Granted: —
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Expires: 2001-10-20
Abstract
Abstract Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of word blocks, each word block being formed of N n-bit words and each word block including a predetermined serial group of m bits forming said synchronizing information, and for de-serializing the incoming digital signal in dependence on the synchronizing information, comprises an m-stage shift register (2) through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, the first shift register (2) supplying a pulse when it holds the predetermined serial group of m bits, a frequency divider (9) to derive from the incoming digital signal a word rate clock pulse signal, an n-stage shift register (4) through which each said pulse is stepped at the bit rate of the incoming digital signal, a latch circuit (10) synchronized with the word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of the shift register (4), comparators (16 to 19) comparing each phase word with at least one other phase word derived N or an integral multiple of N word periods of the incoming digital signal earlier, the comparators (16 to 19) supplying a control signal only when at least one of the comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of this bit in the phase words indicating the phasing of the word rate clock pulse signal relative to the words of the incoming digital signal, and circuits (5,6,7,24) to de-serialize the incoming digital signal into parallel-bit n-bit words under control of the control signal.
Inventors
- 👤 John Goodwin Spencer Ive
- 👤 Alan Clive Thirlwall
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 05:09
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/08; G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/18; G11B20/1806; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/935; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
318 words
Apparatus for extracting synchronizing information from an incoming serial-bit digital signal formed of a sequence of word blocks each word block being formed of N n-bit words and each word block including a predetermined serial group of m bits forming said synchronizing information and for de-serializing said incoming digital signal in dependence on said synchronizing information, the apparatus comprising: a first shift register arrangement (2, 3) including a first m-stage shift register (2) through which said incoming digital signal is stepped at the bit rate of said incoming digital signal, said first shift register arrangement (2, 3) supplying a pulse when said first shift register holds said predetermined serial group of m bits; means (9) to derive from said incoming digital signal a word rate clock pulse signal; a second shift register arrangement (4, 10, 11) including a second n-stage shift register (4) through which each said pulse is stepped at the bit rate of said incoming digital signal, and latch means (10) synchronized with said word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of said second shift register (4); comparator means (16 to 19) for effectively comparing each said phase word with at least one other said phase word derived N word periods or an integral multiple of N word periods of said incoming digital signal earlier; said comparator means (16 to 19) supplying a control signal only when at least one of said comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of said bit in said phase words indicating the phasing of said word rate clock pulse signal relative to the words of said incoming digital signal; and means (5, 6, 7, 24) to de-serialize said incoming digital signal into parallel-bit n-bit words under control of said control signal.
Claim 2
Dependent Claim
318 words
Apparatus for extracting synchronizing information from an incoming serial-bit digital signal formed of a sequence of word blocks each word block being formed of N n-bit words and each word block including a predetermined serial group of m bits forming said synchronizing information and for de-serializing said incoming digital signal in dependence on said synchronizing information, the apparatus comprising: a first shift register arrangement (2, 3) including a first m-stage shift register (2) through which said incoming digital signal is stepped at the bit rate of said incoming digital signal, said first shift register arrangement (2, 3) supplying a pulse when said first shift register holds said predetermined serial group of m bits; means (9) to derive from said incoming digital signal a word rate clock pulse signal; a second shift register arrangement (4, 10, 11) including a second n-stage shift register (4) through which each said pulse is stepped at the bit rate of said incoming digital signal, and latch means (10) synchronized with said word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of said second shift register (4); comparator means (16 to 19) for effectively comparing each said phase word with at least one other said phase word derived N word periods or an integral multiple of N word periods of said incoming digital signal earlier; said comparator means (16 to 19) supplying a control signal only when at least one of said comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of said bit in said phase words indicating the phasing of said word rate clock pulse signal relative to the words of said incoming digital signal; and means (5, 6, 7, 24) to de-serialize said incoming digital signal into parallel-bit n-bit words under control of said control signal.
Claim 3
Dependent Claim
76 words
Apparatus according to claim 1 wherein said second shift register arrangement (4, 10, 11) further includes a programmable read-only memory (11) for coding said n-bit phase words into respective binary code words each representing a decimal number indicating the position of said bit in said phase word, or if there is no said bit, the absence of any said bit in said phase word; and wherein said comparator means (16 to 19) compares said code words.
Claim 4
Dependent Claim
55 words
Apparatus according to claim 2 wherein said comparator means comprises a plurality of comparators (16 to 19) each able to compare two said code words, and first delay means (12 to 15) for respectively delaying a like plurality of said code words by N, 2N, 3N, ... word periods respectively of said incoming digital signal.
Claim 5
Dependent Claim
12 words
Apparatus according to claim 3 wherein said plurality is equal to four.
Claim 6
Dependent Claim
66 words
Apparatus according to claim 3 or claim 4 wherein said comparator means further comprises evaluation means (21) for evaluating the results of the comparison effected by said plurality of comparators (16 to 19) and for supplying said control signal only when all of said comparators indicate two code words which are identical and correspond to a phase word containing a bit corresponding to a said pulse.
Claim 7
Dependent Claim
16 words
Apparatus according to claim 5 wherein said evaluation means is a further programmable read-only memory (21).
Claim 8
Dependent Claim
68 words
Apparatus according to any one of the preceding claims wherein said first shift register (2) has m outputs coupled to the m stages respectively, some of said outputs being true outputs and the remainder being inverse outputs, and the arrangement being such that when said first shift register (2) holds said predetermined serial group of m bits a like signal is supplied over each one of said outputs.
Claim 9
Dependent Claim
30 words
Apparatus according to claim 7 wherein said outputs of said first shift register (2) are respectively connected to the inputs of an m-input NAND gate (3), which supplies said pulse.
Claim 10
Dependent Claim
131 words
Apparatus according to claim 3 wherein said means (5, 6, 7, 24) to de-serialize said incoming digital signal comprises a first n-input latch circuit (5) the inputs of which are respectively coupled to n of the m stages of said first shift register (2) where m is greater than or equal to n, second delay means (6) coupled to the outputs of said first latch circuit (5) for effecting a delay equal to the maximum delay of said first delay means (6), means (7) for deriving from the output of said second delay means 2n-1 bits in parallel and corresponding to 2n-1 serial bits of said incoming digital signal, and means (24) to select from said 2n-1 bits under control of said control signal the n bits forming one said word.
Claim 11
Dependent Claim
19 words
Apparatus according to any one of the preceding claims wherein said incoming digital signal is a digital television signal.
Claim 12
Dependent Claim
13 words
Apparatus according to any one of the preceding claims wherein n is ten.
Claim 13
Dependent Claim
9 words
Apparatus according to claim 11 wherein m is twelve.
Claim 14
Dependent Claim
12 words
Apparatus according to claim 11 or claim 12 wherein N is sixty-four.
References Cited (Backward Citations)
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