Data storage systems

Claim 1

A data storage system in which fixed length data words, having M-l data byte positions and one word check byte position a "write" block check byte being included periodically, are accessed as such from plural failure independent storage units, (11-0, to 11-14) one byte per unit and including a dual function ECC system for either correcting from a single syndrome byte random 1-bit errors in a data word or multi-bit errors in the same byte position of successive data words, and where each syndrome byte is developed from a write check byte and a read check byte where each bit position of the check bytes represents the modulo-2 sum of the value of data in bit positions defined by ones association in n rows of a arity check matrix H' derived from a parity check matrix H, which itself corresponds to an m-sequence of length 2-1, where b is equal to the number of bit positions in each said byte, by selecting therefrom M|b x b| non-overlapping submatrices spaced apart by (X-b) columns, where λ is greater than b, the ECC system including means (25) for generating a syndrome byte for each word, a comparator (80), a syndrome processing circuit (30) operable to process a non-zero syndrome byte to provide a sequence of different b bit vectors, positionally related-in the m-sequence to the syndrome byte by a factor Kλ where K is the position number in said sequence, means (28) for transferring each non-zero syndrome byte to the processing circuit, and means (39) responsive to the output of the processing circuit to indicate the byte location and error pattern assuming a random single-bit error in the data word producing the processed syndrome and for correcting such error in response thereto, characterised in that there are included (1) means (35) for logging, for the words of a block, the indicated byte location, the single-bit error pattern, and the non-zero syndrome byte for each processed word where a correction was made; (2) means (19) for generating a block syndrome byte which should be related by a linear function to the sum of all errors which occurred in the data byte positions of the processed words, of a block; (3) summing means (in 30) to provide a summed error pattern byte from all the logged single-bit error patterns; said comparator being operable at the end of each block of words for comparing the block syndrome byte with the summed error pattern byte to confirm (or deny) the validity of each single-bit error pattern correction, and (4) the block check bytes are stored as data bytes within the corresponding blocks.

Claim 7

A system as claimed in any of claims 1 to 4 in which X is 17, the m-sequence is generated from any primative polynomial of degree b, each block comprises a plurality N of data words, each of which includes 15 byte positions, all the words including check bytes and the Nth word including the block parity byte position N being selected in accordance with the error characteristics of the memory system.

Claim 8

A system as claimed in any claim in which each failure independent storage units comprises a bubble memory module, each of which has b bubble chips.