Battery saving frequency synthesizer arrangement

Claim 1

A frequency synthesizer comprising: a voltage controlled oscillator (VCO) having a control input and an output; phase-locked loop (PLL) means for (a) comparing a direct or derivative signal output of the VCO with a reference signal and (b) providing a loop control signal related thereto for coupling to the control input of the VCO; means for interrupting power to the phase-locked loop means; and memory means interposed between the phase-locked lop means and the control input of the VCO for sampling the magnitude of loop control signal from the phase-locked loop means while power is applied thereto and providing a memory signal indicative of the sampled magnitude to the control input of the VCO, during the interruption of power so as to control the frequency of the VCO during the interruption of power.

Claim 8

A method for frequency synthesizing using a phase-locked loop synthesizer comprising the steps of: generating, with phase-locked loop means, a loop control signal for use in controlling a voltage controlled oscillator (VCO) associated with the phase-locked loop means; sampling the magnitude of the loop control signal; generating a memory signal indicative of the sampled magnitude of the loop control signal; interrupting power to the phase-locked loop means; and applying the memory signal, simultaneously with the interruption of power, to a control input of the VCO for controlling its frequency during the power interruption.

Claim 9

A method for frequency synthesizing using a phase-locked loop synthesizer comprising the steps of: generating, with phase-locked loop means, a loop control signal for use in controlling a voltage controlled oscillator (VCO) associated with the phase-locked loop means; sampling the magnitude of the loop control signal; generating a memory signal indicative of the sampled magnitude of the loop control signal; interrupting power to the phase-locked loop means; and applying the memory signal, simultaneously with the interruption of power, to a control input of the VCO for controlling its frequency during the power interruption.

Claim 13

A method for frequency synthesizing comprising the steps of: generating, with phase-locked loop means, a loop control signal for use in controlling a voltage controlled oscillator (VCO) associated with the phase-locked loop means; locking the phase-locked loop; decoupling the control input of the VCO from the phase-locked loop means and coupling it instead to the output of a receiver discriminator so that the VCO will be controlled by the discriminator output rather than the loop control signal from the phase-locked loop means; and interrupting power to the phase-locked loop means.

Claim 14

A method for frequency synthesizing comprising the steps of: generating, with phase-locked loop means, a loop control signal for use in controlling a voltage controlled oscillator (VCO) associated with the phase-locked loop means; locking the phase-locked loop; decoupling the control input of the VCO from the phase-locked loop means and coupling it instead to the output of a receiver discriminator so that the VCO will be controlled by the discriminator output rather than the loop control signal from the phase-locked loop means; and interrupting power to the phase-locked loop means.

Claim 15

A method for operating radio communications equipment having a phase-locked loop synthesizer including phase-locked loop (PLL) means and a voltage controlled oscillator (VCO), comprising the steps of: (a) providing a sample and hold circuit coupling the loop control signal output of the PLL means to the control input of the VCO; (b) locking the PLL means to provide a loop control signal to the sample and hold circuit; (c) causing the sample and hold circuit to sample the magnitude of the loop control signal; (d) normally interrupting power to the PLL means and allowing the sample and hold circuit to provide a control signal to the VCO based upon the magnitude of the loop control signal sampled; (e) periodically applying power to the PLL while activating the sample and hold circuit to re-sample the magnitude of the loop control signal from the PLL means; (f) continuously enabling the phase-locked loop and continuously sampling the loop control signal and continuously up-dating the output of the sample and hold signal to the VCO in response to any of the following: (aa) a received command to switch frequency and transmit on the new frequency, (bb) a received command to transmit on the current frequency, (cc) an off-hook condition, or (dd) loss of a received signal, (g) returning to the normally disabled condition of the second step in the absence of the conditions (aa)-(dd) of step 6.

Claim 16

A method for operating radio communications equipment having a phase-locked loop synthesizer including phase-locked loop (PLL) means and a voltage controlled oscillator (VCO), comprising the steps of: (a) providing a sample and hold circuit coupling the loop control signal output of the PLL means to the control input of the VCO; (b) locking the PLL means to provide a loop control signal to the sample and hold circuit; (c) causing the sample and hold circuit to sample the magnitude of the loop control signal; (d) normally interrupting power to the PLL means and allowing the sample and hold circuit to provide a control signal to the VCO based upon the magnitude of the loop control signal sampled; (e) periodically applying power to the PLL while activating the sample and hold circuit to re-sample the magnitude of the loop control signal from the PLL means; (f) continuously enabling the phase-locked loop and continuously sampling the loop control signal and continuously up-dating the output of the sample and hold signal to the VCO in response to any of the following: (aa) a received command to switch frequency and transmit on the new frequency, (bb) a received command to transmit on the current frequency, (cc) an off-hook condition, or (dd) loss of a received signal, (g) returning to the normally disabled condition of the second step in the absence of the conditions (aa)-(dd) of step 6.

Claim 17

A method for operating radio communications equipment having a phase-locked loop synthesizer including phase-locked loop (PLL) means and a voltage controlled oscillator (VCO) wherein the equipment includes a receiving section having a discriminator, comprising the steps of: (a) locking the PLL means to provide a loop control signal to the VCO; (b) normally interrupting power to the PLL means and a coupling signal from the discriminator to the control input of the VCO to control its frequency during the time period when the PLL is disabled; (c) enabling the PLL continuously in response to the occurrence of any of the following.conditions: (aa) a received command calling for a switch in frequency and transmission on the new frequency, (bb) a received command calling for transmission on the current frequency, (cc) an off-hook condition, or (dd) loss of a received signal, (d) returning to the normally PLL disabled state wherein the output of the discriminator drives the VCO in response to the absence of any of the conditions (aa) through (dd) above.

Claim 18

A method for operating radio communications equipment having a phase-locked loop synthesizer including phase-locked loop (PLL) means and a voltage controlled oscillator (VCO) wherein the equipment includes a receiving section having a discriminator, comprising the steps of: (a) locking the PLL means to provide a loop control signal to the VCO; (b) normally interrupting power to the PLL means and a coupling signal from the discriminator to the control input of the VCO to control its frequency during the time period when the PLL is disabled; (c) enabling the PLL continuously in response to the occurrence of any of the following.conditions: (aa) a received command calling for a switch in frequency and transmission on the new frequency, (bb) a received command calling for transmission on the current frequency, (cc) an off-hook condition, or (dd) loss of a received signal, (d) returning to the normally PLL disabled state wherein the output of the discriminator drives the VCO in response to the absence of any of the conditions (aa) through (dd) above.