Signal processing for digital optical disc players

Claim 2

A signal processor comprising: a source of analog input signals, means for generating a signal which compensates for thermal drift of said analog input signals, means for summing and amplifying said analog input signals and said drift compensating signal to obtain an error compensated signal, means for detecting the peak-to-peak voltage of said error compensated signal and for deriving a tracking threshold signal, and means for comparing said error compensated signal with said tracking threshold signal for providing a digital output signal with accurate positive and negative transitions by preserving the dc content of said imput signal.

Claim 3

The signal processor of Claim 1 comprising: means responsive to said summing and amplifying means for compensating for tbehigh frequencyresponse loss of said error compensated signal, and means responsive to said high frequency response means for filtering out high frequency noise.

Claim 4

The signal processor of Claim 1 wherein said peak-to-peak detecting means -tracks the positive and negative peaks of said analog input signal, means for summing and dividing said positive and negative peak signals to obtain an average of said peak-to-peak analog input signals, and means responsive to said summing and dividing means for filtering said average peak-to-peak analog input signals above the cutoff of said periodically drifting analog input signal to provide a reference voltage to said comparing means in order to determine the digital threshold signal output.

Claim 5

The signal processor of Claim 3 comprising: a reference voltage source, means responsive to said reference voltage source and said filtering means for providing a difference signal, and a further means for filtering said difference signal at a cutoff below the frequency of said periodic drift analog input signal to provide said feedback signal for compensating for thermal drift.

Claim 6

A dc coupled signal processor comprising: a source of analog input signals, a summing amplifier for amplifying said analog input signal and a feedback signal to obtain an error compensated signal, a linear phase amplitude equalizer connected to said summing amplifier for compensating for high frequency response losses, a first low pass filter connected to said linear phase amplitude equalizer for filtering out high frequency noise, an amplifier and driver connected to said first low pass filter for amplifying the output signal of said first low pass filter, a comparator having an outputof said amplifier driver connected to its positive terminal, a peak-to-peak detector connected to the output of said amplifier driver for tracking the positive and negative peaks of said analog signal to provide an average peak-to-peak signal as an output, an adder and divider circuit connected to said peak-to-peak detector for adding the positive and negative peak signals and dividing said signals, a second low pass filter connected to said adder divider circuit having a cutoff frequency above the periodic drift signal of said analog input signal for providing a tracking signal to the negative terminal of said comparator, said comparator comparing the signals at its positive and negative terminals as slicer signals and providing at its . output a digital signal with accurate positive and negative transitions, a difference amplifier having an output of said second low pass filter connected to its positive input terminal and a reference voltage connected to its negative input terminal to provide a difference signal of the average peak-to-peak signal, and a third low pass filter connected to said difference amplifier having a cutoff frequency below the frequency of said analog input signal for providing a feedback signal compensated for drift to said summing amplifier.

Claim 7

A dc coupled signal processor comprising: a source of analog input signals, a summing amplifier for amplifying said analog input signal and a feedback signal to obtain an error compensated signal, a linear phase amplitude equalizer connected to said summing amplifier for compensating for high frequency response losses, a first low pass filter connected to said linear phase amplitude equalizer for filtering out high frequency noise, an amplifier and driver connected to said first low pass filter for amplifying the output signal of said first low pass filter, a comparator having an outputof said amplifier driver connected to its positive terminal, a peak-to-peak detector connected to the output of said amplifier driver for tracking the positive and negative peaks of said analog signal to provide an average peak-to-peak signal as an output, an adder and divider circuit connected to said peak-to-peak detector for adding the positive and negative peak signals and dividing said signals, a second low pass filter connected to said adder divider circuit having a cutoff frequency above the periodic drift signal of said analog input signal for providing a tracking signal to the negative terminal of said comparator, said comparator comparing the signals at its positive and negative terminals as slicer signals and providing at its . output a digital signal with accurate positive and negative transitions, a difference amplifier having an output of said second low pass filter connected to its positive input terminal and a reference voltage connected to its negative input terminal to provide a difference signal of the average peak-to-peak signal, and a third low pass filter connected to said difference amplifier having a cutoff frequency below the frequency of said analog input signal for providing a feedback signal compensated for drift to said summing amplifier.