Patent EP0051292A2 successfully refreshed from Google Patents.
EP0051292A2
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EP
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Display device
Assignee: Toshiba Corp
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Filing: 1981-10-29
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Granted: —
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Expires: 2001-10-29
Abstract
Abstract The picture information are stored into a plurality of memory chips (61-11 to 61-44) arranged in a matrix fashion and with plurality of random accessible addresses. The memory chips (61-11 to 61-44) are accessed by a chip select signal formed of a picture information display angle designating signal (R) and an information read out clock signal (D, E), and address designating signals in row and column directions. The picture information are read out and displayed by a CRT display unit (16) in a direction designated by a display angle designating signal.
Inventors
- 👤 Kazuhiko Iida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:40
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/32358; H04N1/32459; H04N1/3247; G; G06; G06T; G06T1/00; G06T1/0007; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/395; H04N1/387; H04N1/3877; H04N2201/00; H04N2201/0077; H04N2201/0081; H04N2201/0082; H04N2201/0089; H04N2201/32; H04N2201/3285; H04N2201/3287
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
124 words
A display device comprising a plurality of memory chips (61-11 to 61-44) for storing the picture information arranged in a matrix fashion and with a plurality of random accessible addresses, means (62 to 67, 70) for supplying chip select signals in succession to those memory chips (61-11 to 61-44) in accordance with a picture display angle designating signal (R) and an information read out clock signal (D, E), means (62 to 69) for addressing in a given sequence an address in the selected memory chip in response to the picture display angle designating signal (R) and the information read out clock signal (D, E), and a display unit (16) for displaying the picture information read out by the address designating means (62 to 69).
Claim 2
Dependent Claim
124 words
A display device comprising a plurality of memory chips (61-11 to 61-44) for storing the picture information arranged in a matrix fashion and with a plurality of random accessible addresses, means (62 to 67, 70) for supplying chip select signals in succession to those memory chips (61-11 to 61-44) in accordance with a picture display angle designating signal (R) and an information read out clock signal (D, E), means (62 to 69) for addressing in a given sequence an address in the selected memory chip in response to the picture display angle designating signal (R) and the information read out clock signal (D, E), and a display unit (16) for displaying the picture information read out by the address designating means (62 to 69).
Claim 3
Dependent Claim
105 words
A display device according to claim 1, wherein said chip select signal supply means (61 to 67, 70) includes a first decoder (62) for forming an angle signal from said picture display angle designating signal, a selector circuit (63) for selectively producing said information read out clock signal (D, E) in accordance with a given angle signal from said first decoder (62), a counter (65, 67) for counting said clock signal (D, E) from said selector circuit (63), and a second decoder (70) which receives the output signal from said counter (65, 67) and said angle designating signal (R) to form a chip select signal.
Claim 4
Dependent Claim
113 words
A display device according to claim 1, wherein said address designating means (62, 69) includes a first decoder (62) for forming an angle signal from said picture information display angle designating signal, a selector circuit (63) for selectively producing said information read out clock signal (D, E) in accordance with a given angle signal from said first decoder (62), a counter (64, 66) for counting said clock signal (D, E) from said selector circuit (63), and first and second gate circuits (68, 69) which receives an output signal from said counter (64, 66) and said given angle signal from said decoder (62) to sequentially produce memory chip address signals in a matrix array.
Claim 5
Dependent Claim
110 words
A display device according to claim 1, further comprising a first refresh memory (75) into which the picture information read out from said memory chips (61-11 to 61-44) are stored, a circuit (77) for determining a phase of the picture information supplied from said refresh memory (75) to said display unit (16), a means (80) for displaying a cursor on a picture displayed by said display unit (16), a second refresh memory (76) for storing the picture information when the picture information within a cursor displayed are converted, and means (102) for switching the picture information of said display unit (16) between said first and second refresh memories (75, 76).
References Cited (Backward Citations)
No citation records indexed.
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