EP0051158A1
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Electrically alterable double dense memory
Assignee: International Business Machines Corp
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Filing: 1981-10-05
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Granted: —
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Expires: 2001-10-05
Abstract
Abstract An electrically alterable double dense memory is provided which includes a field effect transistor (10) having first and second spaced apart diffusion regions (14, 16) of a first conductivity defining a channel region (18)at the surface of a semiconductor substrate (12) having a second conductivity. First and second floating gates (22, 24) are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region (18). First and second dual charge injector structures (26, 36) or enhanced conduction insulators are disposed between the first and second floating gates (22, 24) and a common control gate (28) of the transistor. A word line (WL1) is connected to the control gate (28) and first and second bit lines (BL1, BL2) are connected to the first and second diffusion regions (14, 16). By applying (48, 50) appropriate pulses to the word and bit , lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region (18) associated with the selected floating gate and then discharged at will. In this manner binary digits of information are stored in each of the two floating gates (22, 24) and altered as desired. By applying (48) appropriate voltages to the control gate and to one of the first and second diffusion regions (14, 16), the stored information or charge condition of the floating gate associated with the other of the first and second diffusion regions can be determined.
Inventors
- 👤 Harish Narandas Kotecha
- 👤 Jr. Wendell Phillips Noble
- 👤 Francis Walter Wiedman Iii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 03:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; H10D30/60; H10D30/68; H10D30/681; H10D30/682
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
97 words
An integrated electrically alterable double dense memory comprising: a field effect transistor (10) having first (14) and second (16) spaced apart diffusion regions defining a channel region (18) having first and second ends and a control gate (28), first (22) and second (24) charge trapping regions disposed over the first and second ends, respectively, of said channel region (18), means (48, 50) for applying control pulses to said control gate (28) for selectively controlling charge on said first and second floating gates, and means for sensing current flow between said first and second diffusion regions (22, 24).
Claim 2
Dependent Claim
97 words
An integrated electrically alterable double dense memory comprising: a field effect transistor (10) having first (14) and second (16) spaced apart diffusion regions defining a channel region (18) having first and second ends and a control gate (28), first (22) and second (24) charge trapping regions disposed over the first and second ends, respectively, of said channel region (18), means (48, 50) for applying control pulses to said control gate (28) for selectively controlling charge on said first and second floating gates, and means for sensing current flow between said first and second diffusion regions (22, 24).
Claim 3
Dependent Claim
47 words
A memory as set forth in Claim 1 further including a first charge injector (26) disposed between said first charge trapping region (22) and said control gate (28) and a second charge injector (36) disposed between said second charge trapping region (24) and said control gate (28).
Claim 4
Dependent Claim
21 words
A memory as set forth in Claim 2 wherein said first and second charge trapping regions (22, 24) are floating gates.
Claim 5
Dependent Claim
25 words
A memory as set forth in Claim 2 wherein each of said first and second charge injector (26, 36) is a single charge injector system.
Claim 6
Dependent Claim
26 words
A memory as set forth in Claim 2 wherein each of said first and second charge injector systems (26, 36) is a dual charge injector system.
Claim 7
Dependent Claim
44 words
A memory as set forth in Claims 1 to 5 wherein each of said first and second charge injector systems (26, 36) includes first and second silicon-rich silicon dioxide layers (30, 32) and a dielectric film (34) interposed between said first and second layers.
Claim 8
Dependent Claim
44 words
A memory as set forth in Claims 3 and 6 wherein said first and second floating gates (22, 24) and said control gate (28) are disposed along said channel region with said control gate (28) being disposed between said first and second floating gates.
Claim 9
Dependent Claim
27 words
A memory as set forth in Claim 7 wherein said first and second floating gates (22, 24) and said control gate (28) are made of doped polysilicon.
Claim 10
Dependent Claim
188 words
A memory as set forth in Claim 1 wherein said first and second charge trapping regions (22, 24) are first and second floating gates, respectively, and further including atfirst dielectric layer (30) disposed between said first floating gate (22) and said control gate (28), a second dielectric layer (38) disposed between said second floating gate (24) and said control gate (28), a third dielectric layer (32) disposed between said first floating gate and said first diffusion region and a fourth dielectric layer (40) disposed between said second floating gate and said second diffusion region and wherein said first floating gate, said first dielectric layer and said control gate form a first capacitor and said first floating gate, said third dielectric layer and said first diffusion region form a second capacitor having a capacitance substantially larger than the capacitance of said first capacitor, said second floating gate, said second dielectric layer and said control gate form a third capacitor and said second floating gate, said fourth dielectric layer and said second diffusion region form a fourth capacitor having a capacitance substantially larger than the capacitance of said third capacitor.
Claim 11
Dependent Claim
33 words
A memory as set forth in Claim 9 wherein said control pulse applying means (48, 50) applies pulses to said control gate (28) and to said first and second floating gates (22, 24).
Claim 12
Dependent Claim
93 words
A memory as set forth in claims 1 to 10 comprising: a field effect transistor having a channel region (18) formed between first and second spaced apart diffusions (14, 16), a control gate and first and second floating gates disposed over said first and second diffusions, respectively, and extending over said channel region, t. means (48, 50) for applying control pulses to said control gate for selectively controlling charge on said first and second floating gates (22, 24), and means (48) for sensing current flow between said first and second diffusions (14, 16).
Claim 13
Dependent Claim
202 words
A memory as set forth in Claims 1 to 11 comprising: an array of first, second, third and fourth field effect transistors (Tl - T4), each transistor having first and second spaced apart diffusion regions defining a channel region, a control gate disposed over said channel region and first and second floating gates disposed over said first and second diffusion regions and extending over said channel region, first and second word lines (WLl, WL2), said first word line being connected to the control gate of said first and second transistors, and said second word line being connected to the control gate of said third and fourth transistors, first, second, third and fourth bit lines (BL1 - BL4), said first and second bit lines being connected to the first and second diffusion regions, respectively, of said first and third transistors and said third and fourth bit lines being connected to the first and second diffusion regions, respectively, of said second and fourth transistors, means (50) for applying control pulses to said control gates and to said diffusion regions for selectively controlling charge on said first and second floating gates, and means (48) for sensing current flow between said first and second diffusion regions.
Claim 14
Dependent Claim
105 words
A memory as set forth in Claim 12 wherein each of said transistors further includes a first conduction enhanced insulator (34) disposed between said first floating gate and said control gate and a second conduction enhanced insulator (42) disposed between said second floating gate and said control gate and wherein the capacitance between said first floating gate and said first diffusion region is substantially larger than the capacitance between said first floating gate and said control gate and the capacitance between said second floating gate and said second diffusion region is substantially larger than the capacitance between said second floating gate and said control gate.
References Cited (Backward Citations)
US3750115A
Cited
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