Circuit for correcting error in digital information signal

Claim 1

A circuit for correcting errors in an information signal having been subjected to a time-base variation as well as the errors due to passage of said information signal through a system, said information signal including a plurality of digital signal trains each having digital information data and error correction data with recurrent sync pulses interposed between adjacent two signal trains, the correcting circuit comprising: a source of clock pulses (9); means (11) for generating a correction operation start signal in response to each of said sync pulses; a counter (1) arranged to count the clock pulses from said source during a time period between successive two correction operation start signals from said start signal generating means; storage means (8) including a first storage section serving to store said information signal and a second storage section; a correction operation circuit (4, 6) arranged to be supplied with said information signal from said first storage section and having means for performing a plurality of operation steps for correcting the errors in said information signal with said error correction data, the results of said operation steps being stored in said second storage section; means (3) responsive to the output of said counter for generating an operation timing signal to be supplied to said correction operation circuit so that the performance of said plurality of operation steps are timed with said operation timing signal; means (2) responsive to the output of said counter for monitoring the degree of execution of operation steps in said correction operation circuit; and means (7) responsive to the output of said monitoring means for controlling writing of said operation results in said second storage section.