US3622984A — Error correcting system and method

Claim 1

Independent Claim 109 words

A method of detecting errors occurring in a string of binary data comprising the steps of: processing said data to generate a first check burst including two groups of check bits, the first of said groups representing a function of the information contained in said data, the second of said groups representing the addresses of binary ''''ones'''' in said data; transmitting said check burst with the data; processing said data a second time to generate a second check burst identical with the first for identical data; and comparing said first and second check bursts to detect any differences therein which are indicative of errors in the data being processed.

Claim 2

Independent Claim 109 words

A method of detecting errors occurring in a string of binary data comprising the steps of: processing said data to generate a first check burst including two groups of check bits, the first of said groups representing a function of the information contained in said data, the second of said groups representing the addresses of binary ''''ones'''' in said data; transmitting said check burst with the data; processing said data a second time to generate a second check burst identical with the first for identical data; and comparing said first and second check bursts to detect any differences therein which are indicative of errors in the data being processed.

Claim 3

Dependent Claim 88 words

The method of claim 1 further including the steps of: generating a syndrome having first and second parts by a comparison of corresponding groups of the first and second check bursts, which syndrome is all ''''zeros,'''' if no errors has occurred; shifting the bits of the syndrome parts in serial feedback fashion until the bits of the first part are positioned in a predetermined array; and thereafter decoding said syndrome in accordance with a predetermined logic operation to provide the addresses of the errors occurring in said data.

Claim 4

Dependent Claim 21 words

The method of claim 2 further including the step of inverting the data bit at each address of an indicated error.

Claim 5

Dependent Claim 40 words

The method of claim 2 wherein the predetermined array of the first part of said syndrome comprises a binary ''''one'''' followed by a predetermined number of binary ''''zeros'''' followed by a plurality of binary digits which are ''''ones'''' or ''''zeros.''''

Claim 6

Dependent Claim 60 words

The method of claim 2 wherein the logic operation corresponds to the following functions: a1 b1 a2 b2 (s2.a1) a3 b3 (s3.a1) (s2.(a2 a1)) a4 b4 (s4.a1) (s3.a2) s2.(a3 (a1.a2)) where ai designate the address of the leading error, bi represent bits in the second part of the syndrome and si represent bits in the first part of the syndrome.

Claim 7

Independent Claim 164 words

The method of error checking a string of binary data comprising the steps of: computing a first group of check bits by a cycliC division of said string of data; computing a second group of check bits by adding in incrementally shifted positions the binary representations of the sequential position of each binary bit of one value in said string of data; transmitting said string of binary data including a first check burst comprising the first and second groups of check bits; receiving said transmitted data; computing in identical fashion a second check burst of first and second groups of check bits from said received data; and comparing the first and second check bursts to produce an error syndrome, wherein the presence of a nonzero bit indicates that said received string of data contains at least one error, said error syndrome having two parts corresponding respectively to the comparison of said first groups of check bits and of said second groups of check bits.

Claim 8

Independent Claim 164 words

The method of error checking a string of binary data comprising the steps of: computing a first group of check bits by a cycliC division of said string of data; computing a second group of check bits by adding in incrementally shifted positions the binary representations of the sequential position of each binary bit of one value in said string of data; transmitting said string of binary data including a first check burst comprising the first and second groups of check bits; receiving said transmitted data; computing in identical fashion a second check burst of first and second groups of check bits from said received data; and comparing the first and second check bursts to produce an error syndrome, wherein the presence of a nonzero bit indicates that said received string of data contains at least one error, said error syndrome having two parts corresponding respectively to the comparison of said first groups of check bits and of said second groups of check bits.

Claim 9

Dependent Claim 100 words

The method of claim 6 further including the steps of: responding to a nonzero bit by simultaneously and separately shifting the bits of both parts of said syndrome in serial feedback fashion until the bits of said first part are positioned in a predetermined manner; decoding said parts of said error syndrome by a predetermined logic to thereby determine the address position and pattern of erroneous bits in said received string of data; and inverting the binary bits in the positions in said received string of data indicated by said decoded error syndrome to provide a string of corrected data.

Claim 10

Dependent Claim 148 words

An arrangement for generating a burst of check bits corresponding to particular binary data for use in the detection and correction of errors occurring in the transmission of said data comprising: a feedback shift register and exclusive-OR gate interconnected in a loop for generating a first group of check bits of an error burst corresponding to a function of the information of said binary data; a counter having a predetermined number of positions; means for selectively transferring from said counter the binary representations of the respective positions of binary ''''ones'''' in said data; first and second registers interconnected in a shift configuration for processing said representations to generate a second group of check bits of the error burst and storing them in said second register; and means for combining said first and second groups of check bits of the error burst with said binary data for transmission therewith.

Claim 11

Dependent Claim 148 words

An arrangement for generating a burst of check bits corresponding to particular binary data for use in the detection and correction of errors occurring in the transmission of said data comprising: a feedback shift register and exclusive-OR gate interconnected in a loop for generating a first group of check bits of an error burst corresponding to a function of the information of said binary data; a counter having a predetermined number of positions; means for selectively transferring from said counter the binary representations of the respective positions of binary ''''ones'''' in said data; first and second registers interconnected in a shift configuration for processing said representations to generate a second group of check bits of the error burst and storing them in said second register; and means for combining said first and second groups of check bits of the error burst with said binary data for transmission therewith.

Claim 12

Dependent Claim 35 words

An arrangement in accordance with claim 8 wherein the means for selectively transferring includes means for transforming the data from a plurality of parallel data tracks to a form for processing on a single track.

Claim 13

Dependent Claim 50 words

An arrangement in accordance with claim 8 wherein the feedback shift register and exclusive-OR gate comprise a plurality of feedback shift register and exclusive-OR gate loop combinations for generating check bits to provide information indicative of the particular one of a plurality of parallel data tracks which is generating errors.

Claim 14

Independent Claim 130 words

A system for detecting errors in a string of binary data comprising: first generator means for processing said data to generate a first check burst having a first group of check bits resulting from a cyclic division of said data and a second group of check bits providing representations of the positions of binary ''''ones'''' in said data; second generator means for generating a second check burst corresponding to the first but resulting from a second processing of said binary data; and means for comparing said first and second check bursts by groups to develop a syndrome having groups of bits corresponding to respective groups of bits of said check bursts and providing an indication of the occurrence of errors in said data between the first and second processing thereof.

Claim 15

Independent Claim 130 words

A system for detecting errors in a string of binary data comprising: first generator means for processing said data to generate a first check burst having a first group of check bits resulting from a cyclic division of said data and a second group of check bits providing representations of the positions of binary ''''ones'''' in said data; second generator means for generating a second check burst corresponding to the first but resulting from a second processing of said binary data; and means for comparing said first and second check bursts by groups to develop a syndrome having groups of bits corresponding to respective groups of bits of said check bursts and providing an indication of the occurrence of errors in said data between the first and second processing thereof.

Claim 16

Dependent Claim 53 words

A system in accordance with claim 11 further including means for cycling said second generator until the first group of bits of said syndrome takes the form of a pattern comprising a binary ''''onE'''' followed by a predetermined number of ''''zeros'''' followed by a plurality of binary digits which are ''''ones'''' or ''''zeros.''''

Claim 17

Dependent Claim 43 words

A system in accordance with claim 12 further including: decoding means coupled to said second generator for decoding the cycled error syndrome in accordance with a predetermined logic operation to indicate the address of each of the errors detected in said binary data.

Claim 18

Dependent Claim 63 words

A system in accordance with claim 13 wherein said predetermined logic operation comprises the following logic functions: a1 b1 a2 b2 (s2.a1) a3 b3 (s3.a1) (s2.(a2 a1)) a4 b4 (s4.a1) (s3.a2) s2.(a3 (a1.a2)) where ai designate the address of the leading error, bi represent bits in the second group of the syndrome, and si represent bits in the first group of the syndrome.

Claim 19

Dependent Claim 135 words

A system in accordance with claim 11 wherein each of said first and second generator means comprises: a feedback shift register and exclusive-OR gate in a loop combination for generating the first group of check bits of said check burst corresponding to the information of said binary data; a counter having a predetermined number of positions; means for selectively transferring from said counter the binary representations of the respective positions of binary ''''ones'''' in said data; first and second registers interconnected in a shift configuration for processing said representations to generate the second group of check bits of said check burst and storing them in said second register; and means for transferring said first and second groups of check bits out of the feedback shift register and exclusive-OR gate and the first and second registers.

Claim 20

Dependent Claim 75 words

A system in accordance with claim 15 further including: means in each of said first and second generator means responsive to the counter thereof the receiving data over a number of parallel tracks and processing said parallel data in accordance with a predetermined logic operation to provide a number of outputs equal to the number of positions in said counter plus the logarithm to the base 2 of the number of said parallel data tracks.

Claim 21

Dependent Claim 16 words

A system in accordance with claim 16 wherein said preselected logic operation comprises the following functions:

Claim 22

Dependent Claim 87 words

A system in accordance with claim 11 including additional means in each of said first and second generator means for processing parallel data to develop additional check bits indicative of the particular data track on which detected errors occur comprising: exclusive-OR means for receiving said parallel data tracks and developing particular data combinations; and a plurality of feedback shift register and exclusive-OR gate combinations, one for each of said data combinations, for storing said additional check bits to identify a selected data track for clipping level adjustment.

Claim 23

Dependent Claim 74 words

An arrangement in accordance with claim 15 wherein said counter is advanced only once for each multiple of binary data bits of a selected number, and further comprising: means for computing a particular bit pattern during the decoding of said error syndrome; and means for operating on said pattern and the groups of said syndrome to provide the addresses of the error bits in said binary data in accordance with a predetermined logic operation.

Claim 24

Dependent Claim 16 words

An arrangement in accordance with claim 19 wherein said predetermined logic operation comprises the following functions:

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1974-11-22	1975-05-24	1975-11-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1978-11-22	1979-05-24	1979-11-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1982-11-22	1983-05-24	1983-11-23	$7700.00	Window Closed / Lapsed

Error correcting system and method

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