Patent EP0048610A2 successfully refreshed from Google Patents.
EP0048610A2
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EP
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Semiconductor device and its manufacture
Assignee: Toshiba Corp
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Filing: 1981-09-21
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Granted: —
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Expires: 2001-09-21
Abstract
Abstract A semiconductor device consists of substrate (10), on which are successively deposited: first insulation layer (11,12); a first conductive layer (13) made of doped polycrystalline silicon; a second insulation layer (14); and a second conductive layer (17, 18), one region (17) of which has relatively low conductivity to form resistive elements and the other region (18) of which has relatively high conductivity and is connected in parallel with the first conductive layer (13) through contact holes in the second insulation layer (14). The first conductive layer (13) and the region of the second conduction layer having high conductivity together form low resistivity circuit wiring.
Inventors
- 👤 Shoji Ariizumi
- 👤 Makoto Segawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 15:20
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/40; H10W20/41; H10W20/435; Y; Y10; Y10S; Y10S257/00; Y10S257/927
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
115 words
A semiconductor device having a plurality of semiconductor elements having at least one PN junction, the device comprising a substrate (10; 31), a first insulation layer (11, 12; 30, 32) on the substrate; a first conductive layer (13;34) on the first insulation layer; a second insulation layer (14;36) on the first conductive layer; and a second conductive layer on the second insulation layer, the second conductive layer having at least two regions of which a first region has relatively high conductivity (17;39) and is connected in parallel with the first conductive layer (13;34) through a plurality of contact holes (15;38) and a second region (18;37) of which has relatively low conductivity and forms resistive means.
Claim 2
Dependent Claim
115 words
A semiconductor device having a plurality of semiconductor elements having at least one PN junction, the device comprising a substrate (10; 31), a first insulation layer (11, 12; 30, 32) on the substrate; a first conductive layer (13;34) on the first insulation layer; a second insulation layer (14;36) on the first conductive layer; and a second conductive layer on the second insulation layer, the second conductive layer having at least two regions of which a first region has relatively high conductivity (17;39) and is connected in parallel with the first conductive layer (13;34) through a plurality of contact holes (15;38) and a second region (18;37) of which has relatively low conductivity and forms resistive means.
Claim 3
Dependent Claim
22 words
2 . A semiconductor device according to claim 1, wherein the first and second conductive layers (13;17,18) are made of polycrystalline silicon.
Claim 4
Dependent Claim
30 words
A semiconductor device according to claim 1, wherein one region (39) is made of metal silicide having high melting point and the other region (37) is made of polycrystalline silicon.
Claim 5
Dependent Claim
52 words
A semiconductor device according to any one of the preceding claims, in which the substrate is of one conductivity type, but contains a plurality of regions (N + ) having another conductivity type and operating as source and drain regions of MOS transistors, the second insulation layer (14;36) having substantially uniform thickness.
Claim 6
Dependent Claim
19 words
A semiconductor device according to claim 4, wherein a low conductivity region (18;37) is formed over a MOS transistor.
Claim 7
Dependent Claim
111 words
A memory device comprising a plurality of memory cells for storing information, each memory cell including a plurality of MOS transistors (1-4), and a resistor (18;37) connected to an electrode of a MOS transistor and made of polycrystalline silicon; a word line (7) connected to the memory cells for selecting a desired memory cell, the word line being constituted by two separated conductive layers (13,17; 34,39) connected in parallel; and a data line (8,9) connected to each memory cell through a gate operated by a signal from the word line, the resistor (18;37) and one of the two conductive layers being formed on an insulating layer (14;36) Laving substantially uniform thickness.
Claim 8
Dependent Claim
111 words
A memory device comprising a plurality of memory cells for storing information, each memory cell including a plurality of MOS transistors (1-4), and a resistor (18;37) connected to an electrode of a MOS transistor and made of polycrystalline silicon; a word line (7) connected to the memory cells for selecting a desired memory cell, the word line being constituted by two separated conductive layers (13,17; 34,39) connected in parallel; and a data line (8,9) connected to each memory cell through a gate operated by a signal from the word line, the resistor (18;37) and one of the two conductive layers being formed on an insulating layer (14;36) Laving substantially uniform thickness.
Claim 9
Dependent Claim
29 words
A memory device according to claim 6, wherein the resistor (17) and one (18) of the two conductive layers are made of polycrystalline silicon formed in the same step.
Claim 10
Dependent Claim
16 words
A memory device according to claim 6, wherein the resistor is formed over the MOS transistor.
Claim 11
Dependent Claim
24 words
A memory device according to claim 6, wherein one of the two conductive layers is made of metal silicide (39) having high melting point.
Claim 12
Independent Claim
41 words
A method of manufacturing a semiconductor device including the steps of forming a first insulation layer (11,12; 30,32) on a semiconductor substrate (10; 31); forming a first conductive layer (13;34) on the first insulating layer forming a second insulating layer (14;
Claim 13
Independent Claim
41 words
A method of manufacturing a semiconductor device including the steps of forming a first insulation layer (11,12; 30,32) on a semiconductor substrate (10; 31); forming a first conductive layer (13;34) on the first insulating layer forming a second insulating layer (14;
Claim 14
Dependent Claim
56 words
16) on the first conductive layer; forming a second conductive layer over the second insulating layer, the second conductive layer includes a first region (17;39) connected to the first conductive layer (13;34) in parallel and a second region (18;37) constituting resistive means; and increasing the conductivity of the region connected to the first conductive layer. i
Claim 15
Dependent Claim
56 words
16) on the first conductive layer; forming a second conductive layer over the second insulating layer, the second conductive layer includes a first region (17;39) connected to the first conductive layer (13;34) in parallel and a second region (18;37) constituting resistive means; and increasing the conductivity of the region connected to the first conductive layer. i
Claim 16
Dependent Claim
25 words
A method of manufacturing a semiconductor device according to claim 10, wherein the second region is formed over a circuit element formed in the substrate.
Claim 17
Dependent Claim
21 words
A method of manufacturing a semiconductor device according to claim 10, wherein the first region (17) is made of polycrystalline silicon.
Claim 18
Dependent Claim
26 words
A method of manufacturing a semiconductor device according to claim 10, wherein the first region (39) is made of metal silicide having a high melting point.
Claim 19
Dependent Claim
21 words
A method of manufacturing a semiconductor device according to claim 13, wherein the second region (18;37) is made of polycrystalline silicon.
References Cited (Backward Citations)
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