Active pull-up circuit

Claim 2

An active pull-up circuit comprising: first and second power supplies, the potential of said first power supply being higher than that of said second power supply; an output line; a first means for generating a first clock signal whose potential is the same as a second potential level during the stand-by mode, while it is the same as a first potential level, which is higher than that of said second potential level, during the pull-up mode; a second means for generating a second clock signal whose potential is the same as a third potential level during the stand-by mode, while it is the same as a fourth potential level, which is lower than said third potential level, during the pull-up mode; means, connected to said first power supply and said output line, for pulling-up the potential of said output line; means, connected to said first clock signal generating means and said pulling-up means, for supplying said first clock signal to said pulling-up means; a depletion type MIS transistor having a drain connected to said pulling-up means and said clock signal supplying means, a source connected to said output line and a gate connected to said second clock generating means.

Claim 3

A circuit as set forth in claim 1, wherein said pulling-up means comprises an enhancement type MIS transistor having a drain connected to said first power supply, a source connected to said output line and a gate connected to said clock signal supplying means.

Claim 4

A circuit as set forth in claim 1, wherein said clock signal supplying means comprises a capacitor having a first electrode connected to said first clock generating means and a second electrode connected to said pulling-up means.

Claim 5

A circuit as set forth in claim 1, wherein said first potential level and said third potential level are the same as that of said first power supply, while said second potential level and said fourth potential level are the same as that of said second power supply.

Claim 6

A dynamic memory device comprising: first and second power supplies, the potential of said first power supply being higher than that of said second power supply; a first clock signal generating means for generating a first clock signal whose potential is high during the stand-by mode; a second clock signal generating means for generating a second clock signal whose potential is the same as a second potential level during the stand-by mode, while it is the same as a first potential level, which is higher than that of said second potential level, during the pull-up mode; a third clock signal generating means for generating a third clock signal whose potential is the same as a third potential level during the stand-by mode, while it is the same as a fourth potential level which is lower than that of said third potential level, during the pull-up mode; a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells, arranged at intersections between said word lines and said bit lines; a plurality of precharging means, each connected to said first power supply, to said first clock signal generating means and to one of said bit lines, for precharging said bit lines; a plurality of sense amplifiers, each connected between one pair of said bit lines, for sensing the difference in potential between the pair of said bit lines during the sensing mode; a plurality of active pull-up circuits, each connected to said first power supply, to said second and third clock signal generating means and to one of said bit lines, for pulling up the potentials of said bit lines; and wherein each of said active pull-up circuits comprises: a pulling-up means, connected to said first power supply and one of said bit lines, for pulling up the potential of the bit line; a clock signal supplying means, connected to said second clock signal generating means and said pulling-up means, for supplying said second clock signal to said pulling-up means; and a depletion type MIS transistor having a drain connected to said pul.ling-up means and said clock signal supplying means, a source connected to one of said bit lines and a gate connected to said third clock generating means.

Claim 7

A dynamic memory device comprising: first and second power supplies, the potential of said first power supply being higher than that of said second power supply; a first clock signal generating means for generating a first clock signal whose potential is high during the stand-by mode; a second clock signal generating means for generating a second clock signal whose potential is the same as a second potential level during the stand-by mode, while it is the same as a first potential level, which is higher than that of said second potential level, during the pull-up mode; a third clock signal generating means for generating a third clock signal whose potential is the same as a third potential level during the stand-by mode, while it is the same as a fourth potential level which is lower than that of said third potential level, during the pull-up mode; a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells, arranged at intersections between said word lines and said bit lines; a plurality of precharging means, each connected to said first power supply, to said first clock signal generating means and to one of said bit lines, for precharging said bit lines; a plurality of sense amplifiers, each connected between one pair of said bit lines, for sensing the difference in potential between the pair of said bit lines during the sensing mode; a plurality of active pull-up circuits, each connected to said first power supply, to said second and third clock signal generating means and to one of said bit lines, for pulling up the potentials of said bit lines; and wherein each of said active pull-up circuits comprises: a pulling-up means, connected to said first power supply and one of said bit lines, for pulling up the potential of the bit line; a clock signal supplying means, connected to said second clock signal generating means and said pulling-up means, for supplying said second clock signal to said pulling-up means; and a depletion type MIS transistor having a drain connected to said pul.ling-up means and said clock signal supplying means, a source connected to one of said bit lines and a gate connected to said third clock generating means.

Claim 8

A device as set forth in claim 5, wherein said pulling-up means comprises an enhancement type MIS transistor having a drain connected to said first power supply, a source connected to one of said bit lines and a gate connected to said clock signal supplying means.

Claim 9

A device as set forth in claim 5, wherein said clock signal supplying means comprises a capacitor having a first electrode connected to said second clock generating means and a second electrode connected to said pulling-up means.

Claim 10

A device as set forth in claim 5, wherein said first potential level and said third potential level are the same as that of said first power supply, while said second potential level and said fourth potential.level are the same as that of said second power supply.

Claim 11

A device as set forth in claim 5, wherein the potential of said first clock signal is higher than that of said first power supply during the stand-by mode.

Claim 12

A device as set forth in claim 5, wherein said memory cells are of a one-transistor and one-capacitor type.