Patent EP0043943A2 successfully refreshed from Google Patents.
EP0043943A2
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EP
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Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
Assignee: International Business Machines Corp
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Filing: 1981-06-23
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Granted: —
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Expires: 2001-06-23
Abstract
Abstract method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
Inventors
- 👤 Shakir Ahmed Abbas
- 👤 Ingrid Emese Magdo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:30
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/027; H10D30/0273; H10D64/00; H10D64/01; H10D64/018; H10D64/025; H10D64/027; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10P95/00; H10D30/0217; H10D64/017
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
314 words
Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions (22, 34 ) on a monocrystalline silicon body(10) comprising: forming a first insulating layer(14)on a major surface of silicon body (10); forming on said layer a polycrystalline silicon layer (16); forming openings in polycrystalline silicon layer (16)by reactive ion etching in the areas designated to be the gate regions and the source and drain regions (32, 33) of said integrated circuits which results in the structure having substantially horizontal surfaces (20)and substantially vertical surfaces (21); forming a second insulating layer(22) on both said substantially horizontal surfaces(20) and said substantially vertical surfaces (21); reactive ion etching second insulation layer (22) to substantially remove second insulating layer (22)from the horizontal surfaces (20) and to provide the narrow dimensioned dielectric regions(22),on silicon body (10); thermally oxidizing the surface of silicon body (10)between certain of said narrow dimensioned regions (22)to form the gate dielectrics; removing the remaining polycrystalline silicon layer (16)by etching to leave the narrow dimensioned dielectric regions (22)and gate dielectric on silicon body (10); and forming the sources and drains for that integrated circuits using the narrow dimensioned regions as the mask for the diffusion or ion implantation; or removing first insulating layer(14) some on top of the areas designated to be the source and drain regions (32, 33); forming source and drain regions (32, 33 ) for that integrated circuits using the narrow dimensioned regions (34) as the mask for the diffusion or ion implantations; and removing the remaining polycrystalline silicon layer (16)by etching to leave the narrow dimensioned regions (34) on silicon body (1 0 ); and forming a conductive layer on silicon body(1O) which has portions thereof electrically separated by that narrow dimensioned regions ( 22 , 34 ) for contacting in self-alignment the sources, drains and forming in self-alignment the gate electrodes for that integrated circuits.
Claim 2
Dependent Claim
314 words
Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions (22, 34 ) on a monocrystalline silicon body(10) comprising: forming a first insulating layer(14)on a major surface of silicon body (10); forming on said layer a polycrystalline silicon layer (16); forming openings in polycrystalline silicon layer (16)by reactive ion etching in the areas designated to be the gate regions and the source and drain regions (32, 33) of said integrated circuits which results in the structure having substantially horizontal surfaces (20)and substantially vertical surfaces (21); forming a second insulating layer(22) on both said substantially horizontal surfaces(20) and said substantially vertical surfaces (21); reactive ion etching second insulation layer (22) to substantially remove second insulating layer (22)from the horizontal surfaces (20) and to provide the narrow dimensioned dielectric regions(22),on silicon body (10); thermally oxidizing the surface of silicon body (10)between certain of said narrow dimensioned regions (22)to form the gate dielectrics; removing the remaining polycrystalline silicon layer (16)by etching to leave the narrow dimensioned dielectric regions (22)and gate dielectric on silicon body (10); and forming the sources and drains for that integrated circuits using the narrow dimensioned regions as the mask for the diffusion or ion implantation; or removing first insulating layer(14) some on top of the areas designated to be the source and drain regions (32, 33); forming source and drain regions (32, 33 ) for that integrated circuits using the narrow dimensioned regions (34) as the mask for the diffusion or ion implantations; and removing the remaining polycrystalline silicon layer (16)by etching to leave the narrow dimensioned regions (34) on silicon body (1 0 ); and forming a conductive layer on silicon body(1O) which has portions thereof electrically separated by that narrow dimensioned regions ( 22 , 34 ) for contacting in self-alignment the sources, drains and forming in self-alignment the gate electrodes for that integrated circuits.
Claim 3
Dependent Claim
50 words
Method of claim 1 wherein in the surface of silicon body (10)a pattern of dielectric isolating regions (12)is formed which separates surface regions of silicon body (10)from one another, and wherein the voltage threshold of said surface region is adjusted by ion implantation after forming of first insulating layer (14).
Claim 4
Dependent Claim
32 words
Method of claim 1 wherein the thickness of first insulating layer(14)is the desired thickness of the gate dielectric of said field effect transistor circuits and is ultimately used for said gate dielectric.
Claim 5
Dependent Claim
25 words
Method of claim 1 wherein after reactive ion etching second insulating layer (22)thermally oxidizing said gate regions until the gate dielectrics to the desired thickness.
Claim 6
Dependent Claim
26 words
Method of claim 1 wherein said narrow width dimensioned regions(22)is less than about 1.5 micrometers and said narrow width dimensioned regions (22)are composed of silicon dioxide.
Claim 7
Dependent Claim
32 words
Method of claims 1 and 4 wherein a mask is used to protect the gate dielectric and the source and drain regions (32, 33) during removing the remaining polycrystalline silicon layer (16).
Claim 8
Dependent Claim
265 words
Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions (48, 62) on a monocrystalline silicon body (10)comprising: providing silicon body (10)having a major surface with field effect transistor designated regions of said silicon exposed; forming on said major surface of silicon body (10) a doped polycrystalline silicon layer (40); forming openings in polycrystalline silicon layer (40)by reactive ion etching in the areas designated to be the gate regions of said field effect transistor integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming the gate dielectric for said integrated circuits on the surface of silicon body(10)exposed in said openings; forming the source and drain regions (51, 52) of said integrated circuits by outdiffusing from doped polycrystalline silicon layer (4 0 ); forming a second insulating layer or a second polycrystalline silicon layer (60)and subsequently an insulating layer(62)on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said insulating layer to substantially remove the insulating layer from said horizontal surfaces and to provide narrow dimensioned dielectric regions (48, 62) on silicon body (10); removing the remaining polycrystalline silicon layer (40)or the remaining first and second polycrystalline silicon layers (40, 6 0 ) by etching to leave the narrow dimensioned regions (48, 62) and the gate dielectric on silicon body (10); and forming a conductive layer on silicon body(10)which has portions thereof electrically separated by narrow dimensioned regions (48, 62) for contacting in self-alignment the source and drain elements and forming in self-alignment the gate electrodes for said integrated circuits.
Claim 9
Dependent Claim
265 words
Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions (48, 62) on a monocrystalline silicon body (10)comprising: providing silicon body (10)having a major surface with field effect transistor designated regions of said silicon exposed; forming on said major surface of silicon body (10) a doped polycrystalline silicon layer (40); forming openings in polycrystalline silicon layer (40)by reactive ion etching in the areas designated to be the gate regions of said field effect transistor integrated circuits which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming the gate dielectric for said integrated circuits on the surface of silicon body(10)exposed in said openings; forming the source and drain regions (51, 52) of said integrated circuits by outdiffusing from doped polycrystalline silicon layer (4 0 ); forming a second insulating layer or a second polycrystalline silicon layer (60)and subsequently an insulating layer(62)on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching said insulating layer to substantially remove the insulating layer from said horizontal surfaces and to provide narrow dimensioned dielectric regions (48, 62) on silicon body (10); removing the remaining polycrystalline silicon layer (40)or the remaining first and second polycrystalline silicon layers (40, 6 0 ) by etching to leave the narrow dimensioned regions (48, 62) and the gate dielectric on silicon body (10); and forming a conductive layer on silicon body(10)which has portions thereof electrically separated by narrow dimensioned regions (48, 62) for contacting in self-alignment the source and drain elements and forming in self-alignment the gate electrodes for said integrated circuits.
Claim 10
Dependent Claim
35 words
Method of claim 7 wherein after reactive ion etching said insulating layer, a mask is used to protect second polycrystalline silicon layer (6 0 )on said gate dielectric during removing the remaining polycrystalline silicon layer.
Claim 11
Dependent Claim
291 words
Method for forming a field effect transistor self-aligned dynamic RAM integrated circuit having a pattern of narrow dimensioned dielectric regions (86)on a monocrystalline silicon body (10) comprising: forming a first insulating layer(14)on a major surface of silicon body (10); forming on said layer a polycrystalline silicon layer (16); forming a mask layer(18)on polycrystalline silicon layer(16)which mask layer has openings over the areas in said major surface designated to be the gate, drain and capacitor regions; forming openings in polycrystalline silicon layer (16)by reactive ion etching in the areas designated to be the drain regions of said integrated ciruit which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming the drain regions (82)in said major surface through said openings; providing a blockout mask (80)for the drain regions; forming additional openings in polycrystalline silicon layer(16)by reactive ion etching in the areas designated to be the capacitor and defining the gate region between one of said drain regions (82) and one of the additional openings in said areas designated to be the capacitor; removing blockout mask (80); forming a second insulating layer(86)on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching second insulating layer(86) to substantially remove said second insulating layer from said horizontal surfaces and to provide the narrow dimensioned dielectric regions (86) on silicon body (10); removing the remaining polycrystalline silicon layer (16) by etching to leave the narrow dimensioned regions (86) and said gate and capacitor dielectrics on silicon body (10); and forming a conductive layer on said silicon body (1 0 ) which has portions thereof electrically separated by the narrow dimensioned regions(86)for contacting in self-alignment the drains, and forming in self-alignment the gate electrodes and capacitor electrodes for said integrated circuit.
Claim 12
Dependent Claim
291 words
Method for forming a field effect transistor self-aligned dynamic RAM integrated circuit having a pattern of narrow dimensioned dielectric regions (86)on a monocrystalline silicon body (10) comprising: forming a first insulating layer(14)on a major surface of silicon body (10); forming on said layer a polycrystalline silicon layer (16); forming a mask layer(18)on polycrystalline silicon layer(16)which mask layer has openings over the areas in said major surface designated to be the gate, drain and capacitor regions; forming openings in polycrystalline silicon layer (16)by reactive ion etching in the areas designated to be the drain regions of said integrated ciruit which results in the structure having substantially horizontal surfaces and substantially vertical surfaces; forming the drain regions (82)in said major surface through said openings; providing a blockout mask (80)for the drain regions; forming additional openings in polycrystalline silicon layer(16)by reactive ion etching in the areas designated to be the capacitor and defining the gate region between one of said drain regions (82) and one of the additional openings in said areas designated to be the capacitor; removing blockout mask (80); forming a second insulating layer(86)on both said substantially horizontal surfaces and said substantially vertical surfaces; reactive ion etching second insulating layer(86) to substantially remove said second insulating layer from said horizontal surfaces and to provide the narrow dimensioned dielectric regions (86) on silicon body (10); removing the remaining polycrystalline silicon layer (16) by etching to leave the narrow dimensioned regions (86) and said gate and capacitor dielectrics on silicon body (10); and forming a conductive layer on said silicon body (1 0 ) which has portions thereof electrically separated by the narrow dimensioned regions(86)for contacting in self-alignment the drains, and forming in self-alignment the gate electrodes and capacitor electrodes for said integrated circuit.
Claim 13
Dependent Claim
24 words
Method of claim 9 wherein said conductive layer is composed of a first layer of doped polycrystalline silicon (90)and a second layer of metal.
Claim 14
Dependent Claim
38 words
Method of claim 9 wherein a thin layer of polycrystalline silicon is blanked deposited after the removing of blockout mask(80)to protect the dielectric in said areas designated to be the capacitor during the subsequent reactive ion etching step.
Claim 15
Dependent Claim
117 words
Method of one or several of the proceeding claims wherein the forming a conductive layer includes blanket depositing a layer of aluminum over the narrow dimensioned dielectric regions and areas in between, blanket depositing a layer of plastic material over said layer of aluminum to planarize the surface, reactive ion etching the plastic material together with the aluminum layer until the tops of the narrow dimensioned dielectric regions are reached; or reactive ion etching the plastic material until the peaks of aluminum covering the the narrow dimensioned dielectric regions are reached; removing the peaks of aluminum by etching down to the narrow dimensioned dielectric regions; and removing the remaining plastic material to thereby form the conductive layer.
Claim 16
Dependent Claim
124 words
Field effect transistor self-aligned dynamic RAM integrated circuit structure made according to claims 9 to 11 comprising; a silicon body (10) having said field effect transistor dynamic RAM devices therein with regions of said devices extending to the major surface of silicon body (10); silicon dioxide regions(12)within said body for isolating groupings of said devices from one another; at least some of said groupings of said devices including a PN junction drain and capacitor structure; a pattern of narrow dimensioned dielectric regions (86) on said surface of silicon body (10); and electrical contacts (92, 93) to said drain and capacitor filling the spaces between narrow dimensioned regions (86)and which contacts are self-aligned to said narrow dimensioned regions and substantially planar with said narrow regions.
Claim 17
Dependent Claim
33 words
L4. Field effect transistor integrated circuit structure of claim 13 wherein said electrical contacts (92, 93, 94) are composed of a first layer (90)of doped polycrystalline silicon and a second layer of metal.
Claim 18
Dependent Claim
173 words
Substantially planar self-aligned field effect transistor integrated circuit structure made according to one or several of claims 1 to 8 comprising: a silicon body; a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on the surface of said body forming a portion of said field effect transistor structure between certain of said narrow dimensioned regions; PN junction regions within said body forming a portion of said field effect transistor structure and in close proximity to and associate with the channel under said gate dielectric layer; a layer of doped polycrystalline silicon which is substantially shorter than the height of said certain narrow dimensioned regions on said gate dielectric; and metal electrical contacts to said PN junction regions by filling spaces between said pattern of narrow dimensioned region and to said layer of polycrystalline silicon by filling the spaces between certain of said narrow dimensioned regions which contacts are self-aligned to said narrow dimensioned regions and substantially planar with the tops of said narrow regions.
References Cited (Backward Citations)
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