Patent EP0043942A2 successfully refreshed from Google Patents.
EP0043942A2
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Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions
Assignee: International Business Machines Corp
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Filing: 1981-06-23
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Granted: —
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Expires: 2001-06-23
Abstract
Abstract A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub- micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.
Inventors
- 👤 George Richard Goth
- 👤 Ingrid Emese Magdo
- 👤 Shashi Dhar Malaviya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/20; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
205 words
Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions (56; 88; 104, 105, 106, 109)on a monocrystalline silicon body(50, 51; 71, 73)comprising the follwing steps: a) forming a first insulating layer (52; 77; 77, 100) on a major surface of silicon body(50, 51; 71, 73); b) forming on said layer a polycrystalline silicon layer(53, 82, 102); c) forming openings in polycrystalline silicon layer (53, 82, 102)by reactive ion etching which results in a structure having substantially horizontal surfaces and substantially vertical surfaces; d) forming a second conformal layer(55, 88; 104, 105, 106)on both substantially horizontal surfaces and substantially vertical surfaces; e) reactive ion etching second conformal layer(55; 88; 106)to substantially remove second conformal layer (55; 88; 106)from said horizontal surfaces and to provide the narrow dimensioned dielectric regions (56; 88; 104, 105, 106, 109)on silicon body(50, 51; 71, 73); f) removing the polycrystalline silicon layer(53; 82; 102)by etching to leave narrow dimension dielectric regions(56; 88; 104, 105, 106, 109)on silicon body(50, 51; 71, 73);and , g) forming a conductive layer(57, 94, 113)on silicon body(50, 51; 71, 73)which has portions thereof electrically separated by said narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)for contacting in self-alignment regions of said integrated circuits.
Claim 2
Dependent Claim
205 words
Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions (56; 88; 104, 105, 106, 109)on a monocrystalline silicon body(50, 51; 71, 73)comprising the follwing steps: a) forming a first insulating layer (52; 77; 77, 100) on a major surface of silicon body(50, 51; 71, 73); b) forming on said layer a polycrystalline silicon layer(53, 82, 102); c) forming openings in polycrystalline silicon layer (53, 82, 102)by reactive ion etching which results in a structure having substantially horizontal surfaces and substantially vertical surfaces; d) forming a second conformal layer(55, 88; 104, 105, 106)on both substantially horizontal surfaces and substantially vertical surfaces; e) reactive ion etching second conformal layer(55; 88; 106)to substantially remove second conformal layer (55; 88; 106)from said horizontal surfaces and to provide the narrow dimensioned dielectric regions (56; 88; 104, 105, 106, 109)on silicon body(50, 51; 71, 73); f) removing the polycrystalline silicon layer(53; 82; 102)by etching to leave narrow dimension dielectric regions(56; 88; 104, 105, 106, 109)on silicon body(50, 51; 71, 73);and , g) forming a conductive layer(57, 94, 113)on silicon body(50, 51; 71, 73)which has portions thereof electrically separated by said narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)for contacting in self-alignment regions of said integrated circuits.
Claim 3
Dependent Claim
100 words
Method of claim 1 wherein portions of said first insulating layer(52; 77; 77, 100)are removed between certain of narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)by etching to expose silicon body (50, 51; 71, 73) after removal of second conformal layer (55; 88; 106) from said horizontal surfaces has been accomplished, and forming PN junctions and contact regions in silicon body(5O, 51; 71, 73)between certain of narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)whereby the subsequent forming of conductive layer(57, 94, 113)on silicon body(50, 51; 71, 73)makes ohmic contact to the PN junctions and to the contact regions.
Claim 4
Dependent Claim
54 words
Method of claim 2 wherein the PN junctions are emitters (90; 110)of transistors or elements of field effect transistors and the contact regions are N+ and are the collector contacts(92; 111)for an NPN transistor, or are P+ and two such P+ regions are associated with one another to form contacts to a P resistor.
Claim 5
Dependent Claim
56 words
Method of claim 1 and 2 wherein after removal of portions of first insulating layer(52; 77; 77, 100) between certain of narrow dimensioned dielectric regions (56; 88; 104, 105, 106, 109)by the subsequent forming of conductive layer(57, 94, 113)on silicon body(50, 51; 71, 73) Schottky barrier contacts to said silicon body (50, 51; 71, 73)are formed.
Claim 6
Dependent Claim
144 words
Method of claims 1 to 4 wherein the.forming of conductive layer(57; 94; 113)includes blanket depositing a layer of metal over narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)and areas in between, blanket depositing a layer of plastic material over said layer of metal to planarize the surface, reactive ion etching the plastic material until the peaks of metal(57; 94; 113)covering the narrow dimensioned dielectric regions(56; 88; 10, 105, 106, 109)are reached, removing the peaks of metal(57; 94; 113)by etching down to the narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109), and removing the remaining plastic material which served to mask the underlying regions of metal layer (57; 94; 113)during etching by an oxygen ashing process; or reactive ion etching the plastic material together with metal layer(57; 94; 113)until the tops of the narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)are reached.
Claim 7
Dependent Claim
22 words
Method of claim 5 wherein the plastic material for planarizing the surface of metal layer(57; 94; 113)is a polyimide or a photoresist.
Claim 8
Dependent Claim
11 words
Method of claim 1 wherein polycrystalline silicon layer(53; 82; 102)is undoped.
Claim 9
Dependent Claim
30 words
Method of claim 1 wherein second conformal layer(55; 88) is composed of silicon dioxide or of polycrystalline silicon (106) on top of silicon dioxide (104) and silicon nitride layers (105).
Claim 10
Dependent Claim
86 words
Method of claims 1 and 8 wherein subsequent to forming openings in first polycrystalline silicon layer(53; 82; 102), silicon dioxide (104), silicon nitride (105), and second polycrystalline silicon layer (106)are formed and, subsequent to the reactive ion etching of second polycrystalline silicon layer(106)to substantially remove said second layer from the horizontal surfaces the narrow dimensioned regions(106)are thermally oxidized to convert at least part of the polycrystalline silicon to silicon dioxide layer(109,)to thereby form a composite structure(104, 105, 106, 109)of silicon dioxide, silicon nitride and polycrystalline silicon.
Claim 11
Dependent Claim
21 words
10 Method of claims 1 and 5 wherein conductive layer (57; 94; 113)is composed of aluminum or of doped polycrystalline silicon.
Claim 12
Dependent Claim
29 words
Method of one or several of the preceding claims wherein the narrowest width dimension of said narrow dimensioned dielectric regions(56; 88; 104, 105, 106, 109)is less than 1.5 micrometers.
Claim 13
Dependent Claim
159 words
Method for forming bipolar integrated circuits using a process of one or several of the preceding claims comprising: forming first insulating layer(77)on monocrystalline silicon body(71, 73)having regions of dielectric(75, 76)which separate monocrystalline silicon regions containing a surface base region(80)and a subcollector region (83)from one another; forming polycrystalline silicon layer(82)and forming openings in said layer having substantially horizontal and vertical surfaces(86 and 87),said openings being located at locations above which the emitter(90)and collector contact regions(92)are to be formed; and, forming a second insulating layer(88)and subsequent to reactive ion etching to remove said layer from the horizontal surfaces(86)forming said emitter(90) and collector contact regions(92)through the openings in polycrystalline silicon layer(82, and, subsequent to removal of polycrystalline silicon layer(82)leaving narrow dimensioned dielectric regions (88)forming contact openings in first insulating layer (77)to said emitter(90),base(80)and collector contact regions(83, 92); and, forming conductive layer(94)on silicon body(71, 73) with portions(95, 96, 97)contacting emitter(90),base (80)and collector contact regions(83, 92)which are separated by the narrow dimensioned dielectric regions.
Claim 14
Dependent Claim
61 words
Method of claim 12 wherein openings are formed in polycrystalline silicon layer(82)at locations where Schottky barrier devices are to be formed, protecting such locations during forming the emitter(90) and collector contact region(92h and forming openings in first insulating layer(77)at locations where Schottky barrier devices are to be formed, and by forming conductive layer(97)forming Schottky barrier contacts to silicon body (71, 73).
Claim 15
Dependent Claim
82 words
Method of claim 12 wherein second conformal layer (104, 105, 106)is formed by thermally oxidizing the expose surfaces of first layer of polycrystalline silicon(102), forming a layer of silicon nitride(105) over said silicon dioxide layer(104), and forming a second layer of polycrystalline silicon (106)over said silicon nitride layer (105)and, wherein the surfaces of vertical second layer of polycrystalline silicon(106),remaining after reactive ion etching of said layer, are thermally oxidized to silicon dioxide (109), and forming emitter (110) and collector contact regions (111).
Claim 16
Dependent Claim
33 words
Method of claim 14 wherein resistors R1 and R2 are provided which are P type and wherein two P+ contact regions are formed in the silicon body for contacting said P type resistors.
Claim 17
Dependent Claim
34 words
Method of one or several of the preceding claims wherein NPN transistors, Schottky barrier devices and resistors are so arrenged and inteconnected by conductive layer(113)to form Schottky coupled memory cells in the integrated circuit.
Claim 18
Dependent Claim
143 words
Method of one or several of the preceding claims wherein openings are formed in polycrystalline silicon layer (122)having substantially horizontal and vertical surfaces, said openings being located at locations above which base contacts(128)are to be made to the base region, and the designated emitter(127)and collector contact regions for the bipolar integrated circuit remains covered with polycrystalline silicon layer (121); forming a second insulating layer or a composite layer, and, subsequent to reactive ion etching to remove said layer from the horizontal surfaces and removal of polycrystalline silicon layer(121)by etching, leaving narrow dimensioned dielectric regions(124),forming emitter regions(127)in the surface regions of the silicon body, and forming contact openings in first insulating layer (120)to emitter(127),base, and collector contact regions, and forming conductive layer on the silicon body with portions contacting emitter, base and collector contact regions which are separated by the narrow dimensioned dielectric regions.
Claim 19
Dependent Claim
32 words
Method of claim 17 wherein the narrowest surface dimension of emitter regions(127)is less than 2.5 . micrometers and the narrowest width dimension of the narrow dimensioned dielectric regions(124)is less than 0.3 micrometers.
Claim 20
Dependent Claim
36 words
Method of claim 17 wherein the surface base regions are separated by said dielectric from the associated collector contact regions and certain of the narrow dimensioned dielectric regions bridge across the width of said base regions.
Claim 21
Dependent Claim
103 words
Substantially planar self-aligned integrated circuit structure comprising: a silicon body(50, 51; 71, 73)having electrical devices therein with regions of said devices extending to the major surface of said body; silicon dioxide regions(75, 76)with said body for isolating said electrical devices from one another; a pattern of narrow dimension dielectric regions(56; 88; 104, 105, 106, 109)on said surface of said body; and electrical contacts(58, 61, 63, 64; 95, 96, 97; 113, 114, 115, 116)to said devices filling the spaces between said narrow dimensioned dielectric regions and which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
Claim 22
Dependent Claim
103 words
Substantially planar self-aligned integrated circuit structure comprising: a silicon body(50, 51; 71, 73)having electrical devices therein with regions of said devices extending to the major surface of said body; silicon dioxide regions(75, 76)with said body for isolating said electrical devices from one another; a pattern of narrow dimension dielectric regions(56; 88; 104, 105, 106, 109)on said surface of said body; and electrical contacts(58, 61, 63, 64; 95, 96, 97; 113, 114, 115, 116)to said devices filling the spaces between said narrow dimensioned dielectric regions and which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
References Cited (Backward Citations)
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