Patent US3076369A successfully refreshed from Google Patents.
Patent EP0043720A2 successfully refreshed from Google Patents.
EP0043720A2
Expired / Lapsed
EP
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Error compensation circuit for a bit clock
Assignee: Xerox Corp
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Filing: 1981-07-03
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Granted: —
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Expires: 2001-07-03
Abstract
Abstract Controlling the clock rate separately for each facet of a polygon used in a driven raster output scanner whereby the clock rate for facet zero is served using a first order integrator (11) driven by a digital correction circuit which compares the actual number of pulses against the required number, and produces therefrom an analog correction pulse width which is applied to the integrator (11). A second order integrator (19) is used to compensate for leakage of charge from the parallel capacitor of the first order integrator (11), to improve performance. The remaining facets are then corrected for by assigning to each individual correction voltage. This correction voltage is generated by counting clock pulses for each additional facet and using these pulse totals to generate individual analog correction voltages which are added to, or subtracted from, the facet zero voltage in an adder (18) which combines the facet zero correction voltage with each individual voltage in sequence.
Inventors
- 👤 Ronald E. Rider
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:48
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/04; H04N1/047; H04N1/053; H04N1/113; H04N1/1135; H04N2201/00; H04N2201/024; H04N2201/02406; H04N2201/02439; H04N2201/04; H04N2201/047; H04N2201/04701; H04N2201/0471; H04N2201/04732; H04N2201/04744; H04N2201/04753; H04N2201/04758; H04N2201/04767; H04N2201/04768; H04N2201/04775; H04N2201/04777; H04N2201/04793; H04N2201/04794
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
192 words
A circuit for individually correcting the bit clock of a spot scanner for each of a plurality of facets of a reflective and rotary polygon, characterised by: clock counter means (33) for determining whether the clock pulse count for each scan is too high or too low, and for creating a digital correction signal, facet counter means (31) for associating each facet with its associated digital correction signal, first integrating means (11, 16, 17) for transforming the digital correction signal for facet number zero into a facet zero analog correction voltage, memory means (30) responsive to said clock counter means and addressed by said facet counter means for storing the digital correction signal for each facet other than facet number zero, and responsive to said facet counter means for outputting the digital correction signal for the current facet, a digital-to-analog converter (32) for converting said digital correction signal for the current facet into an analog current facet correction voltage, an adder (18) for adding together said facet zero correction and said current facet correction voltages, and a clock generator (10) responsive to the adder output, for producing pulses at a corrected frequency.
Claim 2
Dependent Claim
192 words
A circuit for individually correcting the bit clock of a spot scanner for each of a plurality of facets of a reflective and rotary polygon, characterised by: clock counter means (33) for determining whether the clock pulse count for each scan is too high or too low, and for creating a digital correction signal, facet counter means (31) for associating each facet with its associated digital correction signal, first integrating means (11, 16, 17) for transforming the digital correction signal for facet number zero into a facet zero analog correction voltage, memory means (30) responsive to said clock counter means and addressed by said facet counter means for storing the digital correction signal for each facet other than facet number zero, and responsive to said facet counter means for outputting the digital correction signal for the current facet, a digital-to-analog converter (32) for converting said digital correction signal for the current facet into an analog current facet correction voltage, an adder (18) for adding together said facet zero correction and said current facet correction voltages, and a clock generator (10) responsive to the adder output, for producing pulses at a corrected frequency.
Claim 3
Dependent Claim
41 words
The circuit of claim 1 characterised by second integrating means (19, 20, 23) responsive to said digital correction signal for producing a compensating voltage which is applied to the input of said first integrating means to compensate for charge leakage therefrom.
Claim 4
Dependent Claim
58 words
The circuit of claim 1 or 2 characterised by a start-of-scan detector and an end-of-scan detector, each comprising a light-sensitive means for determining when the spot passes the respective scan point, the output signals of said detectors being used to start and stop said clock counter means and to provide a clock input to said facet counter means.
Claim 5
Dependent Claim
17 words
The circuit of claim 3. characterised in that said clock generator is started by the start-of-scan signal.
Claim 6
Dependent Claim
171 words
A circuit for generating a stream of clock pulses which are frequency adjusted for facet zero of a scanner polygon, comprising a clock counter means (33) for determining whether the clock generator frequency is matched to the scan time of said facet zero, first integrator means (11, 16, 17) for adding a correction output from said clock counter means to previously- generated corrections, and a variable frequency clock generator (10) controlled by the first integrator means output to produce clock pulses, characterised by : facet counter means (31) for identifying each facet, memory means (30) addressed by said facet counter means for storing a digital correction signal from said clock counter means for each facet, and for outputting said digital correction signal during each associated facet scan time, A digital-to-analog converter (32) to convert said memory means output to an analog current facet correction voltage, and an adder (18) to add said first integrator output to said digital-to-analog converter output prior to the sum being coupled to said clock generator input.
Claim 7
Dependent Claim
171 words
A circuit for generating a stream of clock pulses which are frequency adjusted for facet zero of a scanner polygon, comprising a clock counter means (33) for determining whether the clock generator frequency is matched to the scan time of said facet zero, first integrator means (11, 16, 17) for adding a correction output from said clock counter means to previously- generated corrections, and a variable frequency clock generator (10) controlled by the first integrator means output to produce clock pulses, characterised by : facet counter means (31) for identifying each facet, memory means (30) addressed by said facet counter means for storing a digital correction signal from said clock counter means for each facet, and for outputting said digital correction signal during each associated facet scan time, A digital-to-analog converter (32) to convert said memory means output to an analog current facet correction voltage, and an adder (18) to add said first integrator output to said digital-to-analog converter output prior to the sum being coupled to said clock generator input.
Claim 8
Dependent Claim
52 words
The circuit of claim 5, characterised by a second integrator (19, 20, 23), responsive to the facet zero clock counter means output to produce a voltage level output which is coupled to the input of said first integrator means to prevent charge leakage from said first integrator means between facet zero inputs.
Claim 9
Dependent Claim
32 words
The circuit of claim 6 characterised by start-of-scan and end-of-scan detectors, the outputs of which start and stop said clock counter means and said clock generator, and clock said facet counter means.
Claim 10
Dependent Claim
31 words
The circuit of any preceding claim characterised in that the or each integrator comprises an operational amplifier (11, 19) a series input resistor (16, 23), and a parallel capacitor (17, 20).
Claim 11
Independent Claim
129 words
A method of correcting the clock frequency of a spot scanner for each facet of a rotary polygon characterised by the steps of: counting the clock pulses during the duration of each scan, for facet number zero, raising or lowering a facet zero correction voltage for the duration of the polygon rotation if the pulse count is too high or low, to control the facet number zero clock frequency, for the remainder of the facet scans of the polygon, increasing or decreasing a plurality of stored correction voltages, one for each facet, adding together said facet zero correction voltage and the correction voltage which corresponds to the current facet, and using the added voltages to control the frequency of the clock during each scan other than scan number zero.
Claim 12
Independent Claim
129 words
A method of correcting the clock frequency of a spot scanner for each facet of a rotary polygon characterised by the steps of: counting the clock pulses during the duration of each scan, for facet number zero, raising or lowering a facet zero correction voltage for the duration of the polygon rotation if the pulse count is too high or low, to control the facet number zero clock frequency, for the remainder of the facet scans of the polygon, increasing or decreasing a plurality of stored correction voltages, one for each facet, adding together said facet zero correction voltage and the correction voltage which corresponds to the current facet, and using the added voltages to control the frequency of the clock during each scan other than scan number zero.
Claim 13
Dependent Claim
40 words
The method of claim 9 characterised in that each non-zero facet correction voltage is stored as a digital number, and in that each number is converted to a voltage prior to its being added algebraically to the first correction voltage.
References Cited (Backward Citations)
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